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[AVR] Fix up a few accidentally-regressed Generic CodeGen tests recently broken

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In 85e8e6246e0fcc62ba727e8fb5990f1a632125d0, these tests were modified
to work with AVR, but the regex matchers were finicky and required a
fix forward patch, being this.
This commit is contained in:
Dylan McKay 2021-02-05 04:18:48 +13:00
parent 85de81a5d4
commit 93bf157993
4 changed files with 7 additions and 7 deletions
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4
test/CodeGen/Generic/MIRDebugify/locations-and-values.mir
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@ -9,10 +9,10 @@
define i32 @test(i32 %a, i32 %b) {
%add = add i32 %a, 2
; ALL-NEXT: %add = add i32 %a, 2, !dbg [[L1:![0-9]+]]
; VALUE-NEXT: call {{(addrspace\([0-9]+\))?}} void @llvm.dbg.value(metadata i32 %add, metadata [[add:![0-9]+]], metadata !DIExpression()), !dbg [[L1]]
; VALUE-NEXT: call{{( addrspace\([0-9]+\))?}} void @llvm.dbg.value(metadata i32 %add, metadata [[add:![0-9]+]], metadata !DIExpression()), !dbg [[L1]]
%sub = sub i32 %add, %b
; ALL-NEXT: %sub = sub i32 %add, %b, !dbg [[L2:![0-9]+]]
; VALUE-NEXT: call {{(addrspace\([0-9]+\))?}} void @llvm.dbg.value(metadata i32 %sub, metadata [[sub:![0-9]+]], metadata !DIExpression()), !dbg [[L2]]
; VALUE-NEXT: call{{( addrspace\([0-9]+\))?}} void @llvm.dbg.value(metadata i32 %sub, metadata [[sub:![0-9]+]], metadata !DIExpression()), !dbg [[L2]]
; ALL-NEXT: ret i32 %sub, !dbg [[L3:![0-9]+]]
ret i32 %sub
}

2
test/CodeGen/Generic/MIRStripDebug/all.mir
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@ -11,7 +11,7 @@
call void @llvm.dbg.value(metadata i32 %sub, metadata !11, metadata !DIExpression()), !dbg !13
ret i32 %sub, !dbg !14
}
; CHECK-LABEL: define i32 @test(i32 %a, i32 %b) {{(addrspace\([0-9]+\))?}} {
; CHECK-LABEL: define i32 @test(i32 %a, i32 %b) {{(addrspace\([0-9]+\) )?}}{
; CHECK-NEXT: %add = add i32 %a, 2
; CHECK-NEXT: %sub = sub i32 %add, %b
; CHECK-NEXT: ret i32 %sub

6
test/CodeGen/Generic/MIRStripDebug/dont-strip-real-debug-info.mir
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@ -11,11 +11,11 @@
call void @llvm.dbg.value(metadata i32 %sub, metadata !9, metadata !DIExpression()), !dbg !11
ret i32 %sub, !dbg !12
}
; CHECK-LABEL: define i32 @test(i32 %a, i32 %b) {{(addrspace\([0-9]+\))?}} !dbg !4 {
; CHECK-LABEL: define i32 @test(i32 %a, i32 %b) {{(addrspace\([0-9]+\) )?}}!dbg !4 {
; CHECK-NEXT: %add = add i32 %a, 2, !dbg !10
; CHECK-NEXT: call {{(addrspace\([0-9]+\))?}} void @llvm.dbg.value(metadata i32 %add, metadata !7, metadata !DIExpression()), !dbg !10
; CHECK-NEXT: call{{( addrspace\([0-9]+\))?}} void @llvm.dbg.value(metadata i32 %add, metadata !7, metadata !DIExpression()), !dbg !10
; CHECK-NEXT: %sub = sub i32 %add, %b, !dbg !11
; CHECK-NEXT: call {{(addrspace\([0-9]+\))?}} void @llvm.dbg.value(metadata i32 %sub, metadata !9, metadata !DIExpression()), !dbg !11
; CHECK-NEXT: call{{( addrspace\([0-9]+\))?}} void @llvm.dbg.value(metadata i32 %sub, metadata !9, metadata !DIExpression()), !dbg !11
; CHECK-NEXT: ret i32 %sub, !dbg !12
; CHECK-NEXT: }

2
test/CodeGen/Generic/MIRStripDebug/multiple-moduleflags.mir
View File

@ -11,7 +11,7 @@
call void @llvm.dbg.value(metadata i32 %sub, metadata !11, metadata !DIExpression()), !dbg !13
ret i32 %sub, !dbg !14
}
; CHECK-LABEL: define i32 @test(i32 %a, i32 %b) {{(addrspace\([0-9]+\))?}} {
; CHECK-LABEL: define i32 @test(i32 %a, i32 %b) {{(addrspace\([0-9]+\) )?}}{
; CHECK-NEXT: %add = add i32 %a, 2
; CHECK-NEXT: %sub = sub i32 %add, %b
; CHECK-NEXT: ret i32 %sub