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Simplify printing of ARM shifted immediates.

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Print shifted immediate values directly rather than as a payload+shifter
value pair. This makes for more readable output assembly code, simplifies
the instruction printer, and is consistent with how Thumb immediates are
 displayed.

llvm-svn: 134902
This commit is contained in:
Jim Grosbach 2011-07-11 16:48:36 +00:00
parent 3fe7556c3c
commit 93f2ebb5e7
12 changed files with 22 additions and 58 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
lib/Target/ARM/ARMInstrInfo.td
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@ -434,7 +434,6 @@ def so_imm : Operand<i32>, ImmLeaf<i32, [{
return ARM_AM::getSOImmVal(Imm) != -1;
}]> {
let EncoderMethod = "getSOImmOpValue";
let PrintMethod = "printSOImmOperand";
}
// Break so_imm's up into two pieces. This handles immediates with up to 16

32
lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
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@ -126,38 +126,6 @@ void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
}
}
static void printSOImm(raw_ostream &O, int64_t V, raw_ostream *CommentStream,
const MCAsmInfo *MAI) {
// Break it up into two parts that make up a shifter immediate.
V = ARM_AM::getSOImmVal(V);
assert(V != -1 && "Not a valid so_imm value!");
unsigned Imm = ARM_AM::getSOImmValImm(V);
unsigned Rot = ARM_AM::getSOImmValRot(V);
// Print low-level immediate formation info, per
// A5.2.3: Data-processing (immediate), and
// A5.2.4: Modified immediate constants in ARM instructions
if (Rot) {
O << "#" << Imm << ", #" << Rot;
// Pretty printed version.
if (CommentStream)
*CommentStream << (int)ARM_AM::rotr32(Imm, Rot) << "\n";
} else {
O << "#" << Imm;
}
}
/// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
/// immediate in bits 0-7.
void ARMInstPrinter::printSOImmOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
const MCOperand &MO = MI->getOperand(OpNum);
assert(MO.isImm() && "Not a valid so_imm value!");
printSOImm(O, MO.getImm(), CommentStream, &MAI);
}
// so_reg is a 4-operand unit corresponding to register forms of the A5.1
// "Addressing Mode 1 - Data-processing operands" forms. This includes:
// REG 0 0 - e.g. R5

2
lib/Target/ARM/InstPrinter/ARMInstPrinter.h
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@ -38,8 +38,6 @@ public:
void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printSOImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printSORegOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printAddrMode2Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);

10
test/CodeGen/ARM/constants.ll
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@ -14,31 +14,31 @@ define i32 @f2() {
define i32 @f3() {
; CHECK: f3
; CHECK: mov r0, #1, #24
; CHECK: mov r0, #256
ret i32 256
}
define i32 @f4() {
; CHECK: f4
; CHECK: orr{{.*}}#1, #24
; CHECK: orr{{.*}}#256
ret i32 257
}
define i32 @f5() {
; CHECK: f5
; CHECK: mov r0, #255, #2
; CHECK: mov r0, #-1073741761
ret i32 -1073741761
}
define i32 @f6() {
; CHECK: f6
; CHECK: mov r0, #63, #28
; CHECK: mov r0, #1008
ret i32 1008
}
define void @f7(i32 %a) {
; CHECK: f7
; CHECK: cmp r0, #1, #16
; CHECK: cmp r0, #65536
%b = icmp ugt i32 %a, 65536
br i1 %b, label %r, label %r
r:

2
test/CodeGen/ARM/fast-isel.ll
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@ -43,7 +43,7 @@ b1:
br label %b2
; THUMB: add.w {{.*}} #4096
; ARM: add {{.*}} #1, #20
; ARM: add {{.*}} #4096
b2:
%b = add i32 %tmp, 4095

4
test/CodeGen/ARM/fp.ll
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@ -42,7 +42,7 @@ entry:
define double @h(double* %v) {
;CHECK: h:
;CHECK: vldr.64
;CHECK: vldr.64
;CHECK-NEXT: vmov
entry:
%tmp = load double* %v ; <double> [#uses=1]
@ -51,7 +51,7 @@ entry:
define float @h2() {
;CHECK: h2:
;CHECK: mov r0, #254, #10
;CHECK: mov r0, #1065353216
entry:
ret float 1.000000e+00
}

6
test/CodeGen/ARM/long.ll
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@ -14,14 +14,14 @@ entry:
define i64 @f3() {
; CHECK: f3:
; CHECK: mvn r0, #2, #2
; CHECK: mvn r0, #-2147483648
entry:
ret i64 2147483647
}
define i64 @f4() {
; CHECK: f4:
; CHECK: mov r0, #2, #2
; CHECK: mov r0, #-2147483648
entry:
ret i64 2147483648
}
@ -29,7 +29,7 @@ entry:
define i64 @f5() {
; CHECK: f5:
; CHECK: mvn r0, #0
; CHECK: mvn r1, #2, #2
; CHECK: mvn r1, #-2147483648
entry:
ret i64 9223372036854775807
}

4
test/CodeGen/ARM/select-imm.ll
View File

@ -6,7 +6,7 @@ define i32 @t1(i32 %c) nounwind readnone {
entry:
; ARM: t1:
; ARM: mov [[R1:r[0-9]+]], #101
; ARM: orr [[R1b:r[0-9]+]], [[R1]], #1, #24
; ARM: orr [[R1b:r[0-9]+]], [[R1]], #256
; ARM: movgt r0, #123
; ARMT2: t1:
@ -27,7 +27,7 @@ entry:
; ARM: t2:
; ARM: mov r0, #123
; ARM: movgt r0, #101
; ARM: orrgt r0, r0, #1, #24
; ARM: orrgt r0, r0, #256
; ARMT2: t2:
; ARMT2: mov r0, #123

2
test/CodeGen/ARM/select_xform.ll
View File

@ -4,7 +4,7 @@
define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind {
; ARM: t1:
; ARM: sub r0, r1, #6, #2
; ARM: sub r0, r1, #-2147483647
; ARM: movgt r0, r1
; T2: t1:

2
test/CodeGen/ARM/sub.ll
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@ -12,7 +12,7 @@ define i64 @f1(i64 %a) {
; 66846720 = 0x03fc0000
define i64 @f2(i64 %a) {
; CHECK: f2
; CHECK: subs r0, r0, #255, #14
; CHECK: subs r0, r0, #66846720
; CHECK: sbc r1, r1, #0
%tmp = sub i64 %a, 66846720
ret i64 %tmp

7
test/MC/ARM/simple-encoding.ll
View File

@ -39,8 +39,7 @@ define i32 @f3(i32 %a, i32 %b) {
define i32 @f4(i32 %a, i32 %b) {
; CHECK: f4
; CHECK: add r0, r0, #254, #28 @ encoding: [0xfe,0x0e,0x80,0xe2]
; CHECK: @ 4064
; CHECK: add r0, r0, #4064 @ encoding: [0xfe,0x0e,0x80,0xe2]
; CHECK: bx lr @ encoding: [0x1e,0xff,0x2f,0xe1]
%add = add nsw i32 %a, 4064
ret i32 %add
@ -118,7 +117,7 @@ define i32 @f12(i32 %a) {
define i64 @f13() {
; CHECK: f13:
; CHECK: mvn r0, #0 @ encoding: [0x00,0x00,0xe0,0xe3]
; CHECK: mvn r1, #2, #2 @ encoding: [0x02,0x11,0xe0,0xe3]
; CHECK: mvn r1, #-2147483648 @ encoding: [0x02,0x11,0xe0,0xe3]
ret i64 9223372036854775807
}
@ -229,7 +228,7 @@ define i32 @f23(i32 %X, i32 %Y) {
define void @f24(i32 %a) {
; CHECK: f24
; CHECK: cmp r0, #1, #16 @ encoding: [0x01,0x08,0x50,0xe3]
; CHECK: cmp r0, #65536 @ encoding: [0x01,0x08,0x50,0xe3]
%b = icmp ugt i32 %a, 65536
br i1 %b, label %r, label %r
r:

8
test/MC/Disassembler/ARM/arm-tests.txt
View File

@ -1,6 +1,6 @@
# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 | FileCheck %s
# CHECK: addpl r4, pc, #19, #8
# CHECK: addpl r4, pc, #318767104
0x4c 0x45 0x8f 0x52
# CHECK: b #0
@ -21,7 +21,7 @@
# CHECK: mov pc, lr
0x0e 0xf0 0xa0 0xe1
# CHECK: mov pc, #255, #2
# CHECK: mov pc, #3221225535
0xff 0xf1 0xa0 0xe3
# CHECK: movw r7, #4096
@ -72,7 +72,7 @@
# CHECK: movt r8, #65535
0xff 0x8f 0x4f 0xe3
# CHECK: mvnspl r7, #245, #2
# CHECK: mvnspl r7, #1073741885
0xf5 0x71 0xf0 0x53
# CHECK-NOT: orr r7, r8, r7, rrx #0
@ -152,7 +152,7 @@
# CHECK: msr cpsr_fc, r0
0x00 0xf0 0x29 0xe1
# CHECK: msrmi cpsr_c, #241, #8
# CHECK: msrmi cpsr_c, #4043309056
0xf1 0xf4 0x21 0x43
# CHECK: rsbs r6, r7, r8