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[ARM] VMOVN undef folding
If we insert undef using a VMOVN, we can just use the original value in three out of the four possible combinations. Using VMOVT into a undef vector will still require the lanes to be moved, but otherwise the non-undef value can be used.
This commit is contained in:
David Green
parent
cf1a34fda4
commit
941edbe847
@ -15424,6 +15424,14 @@ static SDValue PerformVMOVNCombine(SDNode *N,
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SDValue Op1 = N->getOperand(1);
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unsigned IsTop = N->getConstantOperandVal(2);
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// VMOVNT a undef -> a
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// VMOVNB a undef -> a
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// VMOVNB undef a -> a
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if (Op1->isUndef())
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return Op0;
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if (Op0->isUndef() && !IsTop)
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return Op1;
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// VMOVNt(c, VQMOVNb(a, b)) => VQMOVNt(c, b)
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// VMOVNb(c, VQMOVNb(a, b)) => VQMOVNb(c, b)
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if ((Op1->getOpcode() == ARMISD::VQMOVNs ||
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@ -801,3 +801,144 @@ entry:
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%out = shufflevector <16 x i8> %src1, <16 x i8> undef, <16 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6, i32 8, i32 8, i32 10, i32 10, i32 12, i32 12, i32 14, i32 14>
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ret <16 x i8> %out
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}
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define arm_aapcs_vfpcc <8 x i16> @vmovn32trunct_undef2(<8 x i16> %a) {
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; CHECK-LABEL: vmovn32trunct_undef2:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: bx lr
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;
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; CHECKBE-LABEL: vmovn32trunct_undef2:
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; CHECKBE: @ %bb.0: @ %entry
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; CHECKBE-NEXT: bx lr
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entry:
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%c1 = call <4 x i32> @llvm.arm.mve.vreinterpretq.v4i32.v8i16(<8 x i16> %a)
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%c2 = call <4 x i32> @llvm.arm.mve.vreinterpretq.v4i32.v8i16(<8 x i16> undef)
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%strided.vec = shufflevector <4 x i32> %c1, <4 x i32> %c2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
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%out = trunc <8 x i32> %strided.vec to <8 x i16>
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ret <8 x i16> %out
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}
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define arm_aapcs_vfpcc <8 x i16> @vmovn32trunct_undef1(<8 x i16> %a) {
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; CHECK-LABEL: vmovn32trunct_undef1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmovnt.i32 q0, q0
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; CHECK-NEXT: bx lr
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;
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; CHECKBE-LABEL: vmovn32trunct_undef1:
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; CHECKBE: @ %bb.0: @ %entry
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; CHECKBE-NEXT: vrev64.16 q1, q0
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; CHECKBE-NEXT: vmovnt.i32 q1, q1
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; CHECKBE-NEXT: vrev64.16 q0, q1
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; CHECKBE-NEXT: bx lr
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entry:
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%c1 = call <4 x i32> @llvm.arm.mve.vreinterpretq.v4i32.v8i16(<8 x i16> undef)
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%c2 = call <4 x i32> @llvm.arm.mve.vreinterpretq.v4i32.v8i16(<8 x i16> %a)
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%strided.vec = shufflevector <4 x i32> %c1, <4 x i32> %c2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
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%out = trunc <8 x i32> %strided.vec to <8 x i16>
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ret <8 x i16> %out
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}
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define arm_aapcs_vfpcc <8 x i16> @vmovn16b_undef2(<16 x i8> %a) {
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; CHECK-LABEL: vmovn16b_undef2:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: bx lr
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;
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; CHECKBE-LABEL: vmovn16b_undef2:
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; CHECKBE: @ %bb.0: @ %entry
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; CHECKBE-NEXT: vrev64.8 q1, q0
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; CHECKBE-NEXT: vrev64.16 q0, q1
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; CHECKBE-NEXT: bx lr
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entry:
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%c1 = call <8 x i16> @llvm.arm.mve.vreinterpretq.v8i16.v16i8(<16 x i8> %a)
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%c2 = call <8 x i16> @llvm.arm.mve.vreinterpretq.v8i16.v16i8(<16 x i8> undef)
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%out = shufflevector <8 x i16> %c1, <8 x i16> %c2, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
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ret <8 x i16> %out
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}
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define arm_aapcs_vfpcc <8 x i16> @vmovn16b_undef1(<16 x i8> %a) {
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; CHECK-LABEL: vmovn16b_undef1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: bx lr
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;
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; CHECKBE-LABEL: vmovn16b_undef1:
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; CHECKBE: @ %bb.0: @ %entry
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; CHECKBE-NEXT: vrev64.8 q1, q0
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; CHECKBE-NEXT: vrev64.16 q0, q1
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; CHECKBE-NEXT: bx lr
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entry:
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%c1 = call <8 x i16> @llvm.arm.mve.vreinterpretq.v8i16.v16i8(<16 x i8> undef)
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%c2 = call <8 x i16> @llvm.arm.mve.vreinterpretq.v8i16.v16i8(<16 x i8> %a)
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%out = shufflevector <8 x i16> %c1, <8 x i16> %c2, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
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ret <8 x i16> %out
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}
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define arm_aapcs_vfpcc <8 x i16> @vmovn32_badlanes(<4 x i32> %src1) {
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; CHECK-LABEL: vmovn32_badlanes:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: vmov.16 q1[1], r0
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; CHECK-NEXT: vmov r0, s1
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; CHECK-NEXT: vmov.16 q1[3], r0
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; CHECK-NEXT: vmov.16 q1[5], r0
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; CHECK-NEXT: vmov r0, s2
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; CHECK-NEXT: vmov.16 q1[7], r0
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; CHECK-NEXT: vmov q0, q1
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; CHECK-NEXT: bx lr
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;
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; CHECKBE-LABEL: vmovn32_badlanes:
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; CHECKBE: @ %bb.0: @ %entry
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; CHECKBE-NEXT: vrev64.32 q1, q0
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; CHECKBE-NEXT: vmov r0, s4
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; CHECKBE-NEXT: vmov.16 q2[1], r0
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; CHECKBE-NEXT: vmov r0, s5
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; CHECKBE-NEXT: vmov.16 q2[3], r0
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; CHECKBE-NEXT: vmov.16 q2[5], r0
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; CHECKBE-NEXT: vmov r0, s6
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; CHECKBE-NEXT: vmov.16 q2[7], r0
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; CHECKBE-NEXT: vrev64.16 q0, q2
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; CHECKBE-NEXT: bx lr
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entry:
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%strided.vec = shufflevector <4 x i32> %src1, <4 x i32> undef, <8 x i32> <i32 4, i32 0, i32 5, i32 1, i32 6, i32 1, i32 7, i32 2>
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%out = trunc <8 x i32> %strided.vec to <8 x i16>
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ret <8 x i16> %out
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}
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define arm_aapcs_vfpcc <16 x i8> @vmovn16trunct_undef2(<16 x i8> %a) {
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; CHECK-LABEL: vmovn16trunct_undef2:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: bx lr
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;
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; CHECKBE-LABEL: vmovn16trunct_undef2:
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; CHECKBE: @ %bb.0: @ %entry
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; CHECKBE-NEXT: bx lr
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entry:
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%c1 = call <8 x i16> @llvm.arm.mve.vreinterpretq.v8i16.v16i8(<16 x i8> %a)
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%c2 = call <8 x i16> @llvm.arm.mve.vreinterpretq.v8i16.v16i8(<16 x i8> undef)
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%strided.vec = shufflevector <8 x i16> %c1, <8 x i16> %c2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
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%out = trunc <16 x i16> %strided.vec to <16 x i8>
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ret <16 x i8> %out
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}
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define arm_aapcs_vfpcc <16 x i8> @vmovn16trunct_undef1(<16 x i8> %a) {
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; CHECK-LABEL: vmovn16trunct_undef1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmovnt.i16 q0, q0
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; CHECK-NEXT: bx lr
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;
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; CHECKBE-LABEL: vmovn16trunct_undef1:
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; CHECKBE: @ %bb.0: @ %entry
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; CHECKBE-NEXT: vrev64.8 q1, q0
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; CHECKBE-NEXT: vmovnt.i16 q1, q1
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; CHECKBE-NEXT: vrev64.8 q0, q1
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; CHECKBE-NEXT: bx lr
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entry:
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%c1 = call <8 x i16> @llvm.arm.mve.vreinterpretq.v8i16.v16i8(<16 x i8> undef)
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%c2 = call <8 x i16> @llvm.arm.mve.vreinterpretq.v8i16.v16i8(<16 x i8> %a)
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%strided.vec = shufflevector <8 x i16> %c1, <8 x i16> %c2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
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%out = trunc <16 x i16> %strided.vec to <16 x i8>
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ret <16 x i8> %out
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}
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declare <4 x i32> @llvm.arm.mve.vreinterpretq.v4i32.v8i16(<8 x i16>)
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declare <8 x i16> @llvm.arm.mve.vreinterpretq.v8i16.v16i8(<16 x i8>)
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