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[AMDGPU] Print DWARF register numbers in AMDGPUInstPrinter

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Summary:
Explanation is in a comment in the diff, but essentially printing a
physical register name here is ambiguous. Until we can implement
printing a DWARF register name here just use the encoding directly.

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D76253
This commit is contained in:
Scott Linder 2020-03-16 17:12:09 -04:00
parent c97feb8b52
commit 9435082839
4 changed files with 23 additions and 41 deletions
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14
lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
View File

@ -27,7 +27,19 @@ using namespace llvm;
using namespace llvm::AMDGPU;
void AMDGPUInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
OS << getRegisterName(RegNo);
// FIXME: The current implementation of
// AsmParser::parseRegisterOrRegisterNumber in MC implies we either emit this
// as an integer or we provide a name which represents a physical register.
// For CFI instructions we really want to emit a name for the DWARF register
// instead, because there may be multiple DWARF registers corresponding to a
// single physical register. One case where this problem manifests is with
// wave32/wave64 where using the physical register name is ambiguous: if we
// write e.g. `.cfi_undefined v0` we lose information about the wavefront
// size which we need to encode the register in the final DWARF. Ideally we
// would extend MC to support parsing DWARF register names so we could do
// something like `.cfi_undefined dwarf_wave32_v0`. For now we just live with
// non-pretty DWARF register names in assembly text.
OS << RegNo;
}
void AMDGPUInstPrinter::printInst(const MCInst *MI, uint64_t Address,

1
lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp
View File

@ -43,6 +43,7 @@ AMDGPUMCAsmInfo::AMDGPUMCAsmInfo(const Triple &TT,
WeakRefDirective = ".weakref\t";
//===--- Dwarf Emission Directives -----------------------------------===//
SupportsDebugInformation = true;
DwarfRegNumForCFI = true;
}
bool AMDGPUMCAsmInfo::shouldOmitSectionDirective(StringRef SectionName) const {

12
test/DebugInfo/AMDGPU/print-reg-name.s
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@ -1,10 +1,16 @@
; RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=asm %s | FileCheck %s
; Check that we can print symbolic register operands in CFI instructions.
; FIXME: Currently we can't print register names in CFI directives
; without extending MC to support DWARF register names that are distinct
; from physical register names.
.text
f:
.cfi_startproc
; CHECK: .cfi_undefined s0
.cfi_undefined s0
; CHECK: .cfi_undefined 2560
.cfi_undefined 2560
; FIXME: Until we implement a distinct set of DWARF register names we
; will continue to parse physical registers and pick an arbitrary encoding.
; CHECK: .cfi_undefined 2560
.cfi_undefined v0
.cfi_endproc

37
test/DebugInfo/AMDGPU/register-mapping.s
View File

@ -1,37 +0,0 @@
; RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx1010 -filetype=obj %s | llvm-dwarfdump -debug-frame - | FileCheck %s
; Check that we implement the DWARF register mapping.
.text
f:
.cfi_startproc
; CHECK: CIE
; CHECK: Return address column: 16
; CHECK: FDE
; CHECK: DW_CFA_undefined: reg16
.cfi_undefined pc
; CHECK: DW_CFA_undefined: reg17
.cfi_undefined exec
; CHECK: DW_CFA_undefined: reg32
.cfi_undefined s0
; CHECK: DW_CFA_undefined: reg95
.cfi_undefined s63
; CHECK: DW_CFA_undefined: reg1088
.cfi_undefined s64
; CHECK: DW_CFA_undefined: reg1129
.cfi_undefined s105
; CHECK: DW_CFA_undefined: reg2560
.cfi_undefined v0
; CHECK: DW_CFA_undefined: reg2815
.cfi_undefined v255
; CHECK: DW_CFA_undefined: reg3072
.cfi_undefined a0
; CHECK: DW_CFA_undefined: reg3327
.cfi_undefined a255
.cfi_endproc