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[SystemZ] Don't drop any operands in expandZExtPseudo()
Make sure that any operands, e.g. of an implicit def of a super reg is transferred to the new instruction. Review: Ulrich Weigand llvm-svn: 298484
This commit is contained in:
Jonas Paulsson
parent
ea1106a14e
commit
946a6fbc82
@ -23,7 +23,6 @@
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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@ -221,9 +220,15 @@ void SystemZInstrInfo::expandLOCRPseudo(MachineInstr &MI, unsigned LowOpcode,
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// are low registers, otherwise use RISB[LH]G.
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void SystemZInstrInfo::expandZExtPseudo(MachineInstr &MI, unsigned LowOpcode,
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unsigned Size) const {
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MachineInstrBuilder MIB =
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emitGRX32Move(*MI.getParent(), MI, MI.getDebugLoc(),
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MI.getOperand(0).getReg(), MI.getOperand(1).getReg(), LowOpcode,
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Size, MI.getOperand(1).isKill(), MI.getOperand(1).isUndef());
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// Keep the remaining operands as-is.
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for (unsigned I = 2; I < MI.getNumOperands(); ++I)
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MIB.add(MI.getOperand(I));
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MI.eraseFromParent();
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}
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@ -263,7 +268,8 @@ void SystemZInstrInfo::expandLoadStackGuard(MachineInstr *MI) const {
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// are low registers, otherwise use RISB[LH]G. Size is the number of bits
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// taken from the low end of SrcReg (8 for LLCR, 16 for LLHR and 32 for LR).
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// KillSrc is true if this move is the last use of SrcReg.
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void SystemZInstrInfo::emitGRX32Move(MachineBasicBlock &MBB,
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MachineInstrBuilder
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SystemZInstrInfo::emitGRX32Move(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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const DebugLoc &DL, unsigned DestReg,
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unsigned SrcReg, unsigned LowLowOpcode,
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@ -279,12 +285,11 @@ void SystemZInstrInfo::emitGRX32Move(MachineBasicBlock &MBB,
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else if (!DestIsHigh && SrcIsHigh)
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Opcode = SystemZ::RISBLH;
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else {
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BuildMI(MBB, MBBI, DL, get(LowLowOpcode), DestReg)
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return BuildMI(MBB, MBBI, DL, get(LowLowOpcode), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc) | getUndefRegState(UndefSrc));
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return;
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}
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unsigned Rotate = (DestIsHigh != SrcIsHigh ? 32 : 0);
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BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
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return BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
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.addReg(DestReg, RegState::Undef)
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.addReg(SrcReg, getKillRegState(KillSrc) | getUndefRegState(UndefSrc))
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.addImm(32 - Size).addImm(128 + 31).addImm(Rotate);
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@ -19,6 +19,7 @@
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include <cstdint>
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@ -160,10 +161,13 @@ class SystemZInstrInfo : public SystemZGenInstrInfo {
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void expandZExtPseudo(MachineInstr &MI, unsigned LowOpcode,
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unsigned Size) const;
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void expandLoadStackGuard(MachineInstr *MI) const;
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void emitGRX32Move(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineInstrBuilder
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emitGRX32Move(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
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unsigned LowLowOpcode, unsigned Size, bool KillSrc,
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bool UndefSrc) const;
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virtual void anchor();
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protected:
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132
test/CodeGen/SystemZ/expand-zext-pseudo.ll
Normal file
132
test/CodeGen/SystemZ/expand-zext-pseudo.ll
Normal file
@ -0,0 +1,132 @@
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 -verify-machineinstrs | FileCheck %s
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;
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; Test that a def operand of super-reg is not dropped during post RA pseudo
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; expansion in expandZExtPseudo().
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define void @fun_llvm_stress_reduced(i8*, i32*, i64*, i32) {
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; CHECK: .text
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BB:
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%A = alloca i32
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%Sl24 = select i1 undef, i32* %1, i32* %1
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%L26 = load i16, i16* undef
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%L32 = load i32, i32* %Sl24
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br label %CF847
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CF847: ; preds = %CF878, %BB
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%L61 = load i16, i16* undef
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br label %CF878
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CF878: ; preds = %CF847
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%PC66 = bitcast i32* %Sl24 to double*
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%Sl67 = select i1 undef, <2 x i32> undef, <2 x i32> undef
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%Cmp68 = icmp ugt i32 undef, %3
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br i1 %Cmp68, label %CF847, label %CF863
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CF863: ; preds = %CF878
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%L84 = load i16, i16* undef
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br label %CF825
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CF825: ; preds = %CF825, %CF863
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%Sl105 = select i1 undef, i1 undef, i1 undef
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br i1 %Sl105, label %CF825, label %CF856
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CF856: ; preds = %CF856, %CF825
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%Cmp114 = icmp ult i16 -24837, %L61
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br i1 %Cmp114, label %CF856, label %CF875
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CF875: ; preds = %CF856
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%Shuff124 = shufflevector <2 x i32> undef, <2 x i32> undef, <2 x i32> <i32 1, i32 3>
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%PC126 = bitcast i32* %A to i64*
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br label %CF827
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CF827: ; preds = %CF923, %CF911, %CF875
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%Sl142 = select i1 undef, i64 undef, i64 -1
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%B148 = sdiv i32 409071, 409071
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%E153 = extractelement <2 x i32> %Shuff124, i32 1
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br label %CF911
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CF911: ; preds = %CF827
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br i1 undef, label %CF827, label %CF867
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CF867: ; preds = %CF911
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br label %CF870
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CF870: ; preds = %CF870, %CF867
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store i8 0, i8* %0
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%FC176 = fptoui double undef to i1
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br i1 %FC176, label %CF870, label %CF923
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CF923: ; preds = %CF870
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%L179 = load i16, i16* undef
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%Sl191 = select i1 undef, i64* %PC126, i64* %PC126
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br i1 false, label %CF827, label %CF828
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CF828: ; preds = %CF905, %CF923
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%B205 = urem i16 -7553, undef
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%E209 = extractelement <2 x i32> %Sl67, i32 1
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%Cmp215 = icmp ugt i16 %L179, 0
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br label %CF905
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CF905: ; preds = %CF828
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%E231 = extractelement <4 x i1> undef, i32 1
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br i1 %E231, label %CF828, label %CF829
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CF829: ; preds = %CF909, %CF829, %CF905
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%B234 = udiv i16 %L26, %L84
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br i1 undef, label %CF829, label %CF894
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CF894: ; preds = %CF894, %CF829
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store i64 %Sl142, i64* %Sl191
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%Sl241 = select i1 %Cmp114, i1 false, i1 %Cmp215
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br i1 %Sl241, label %CF894, label %CF907
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CF907: ; preds = %CF894
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%B247 = udiv i32 0, %E153
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%PC248 = bitcast i64* %2 to i8*
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br label %CF909
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CF909: ; preds = %CF907
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store i1 %FC176, i1* undef
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%Cmp263 = icmp ugt i1 undef, %Sl241
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br i1 %Cmp263, label %CF829, label %CF830
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CF830: ; preds = %CF909
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%B304 = urem i16 %L84, %B205
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%I311 = insertelement <2 x i32> %Shuff124, i32 %B247, i32 1
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store i8 0, i8* %0
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%Sl373 = select i1 %Cmp68, i32 0, i32 %E153
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br label %CF833
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CF833: ; preds = %CF880, %CF830
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br label %CF880
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CF880: ; preds = %CF833
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%Cmp412 = icmp ne i16 %B234, -18725
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br i1 %Cmp412, label %CF833, label %CF865
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CF865: ; preds = %CF880
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store double 0.000000e+00, double* %PC66
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br label %CF860
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CF860: ; preds = %CF860, %CF865
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store i8 0, i8* %PC248
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%Cmp600 = icmp sge i32 %B148, undef
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br i1 %Cmp600, label %CF860, label %CF913
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CF913: ; preds = %CF860
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store i32 %E209, i32* undef
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store i32 %Sl373, i32* undef
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%Cmp771 = icmp ule i32 undef, %L32
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br label %CF842
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CF842: ; preds = %CF925, %CF913
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br label %CF925
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CF925: ; preds = %CF842
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%Cmp778 = icmp sgt i1 %Cmp771, %Sl241
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br i1 %Cmp778, label %CF842, label %CF898
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CF898: ; preds = %CF925
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%Sl785 = select i1 %Cmp600, i16 undef, i16 %B304
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unreachable
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}
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