RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 19:23:23 +01:00
Code Issues Projects Releases Wiki Activity

[SelectionDAG] Use various APInt methods to reduce temporary APInt creation

Browse Source 
This patch uses various APInt methods to reduce the number of temporary APInts. These were all found while working through converting SelectionDAG's computeKnownBits to also use the KnownBits struct recently added to the ValueTracking version.

llvm-svn: 301618
This commit is contained in:
Craig Topper 2017-04-28 04:57:59 +00:00
parent 18821e6e59
commit 946fd240da
6 changed files with 30 additions and 39 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -5710,7 +5710,7 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
if (UnknownBits == 0) return DAG.getConstant(1, SDLoc(N0), VT);
// Otherwise, check to see if there is exactly one bit input to the ctlz.
if ((UnknownBits & (UnknownBits - 1)) == 0) {
if (UnknownBits.isPowerOf2()) {
// Okay, we know that only that the single bit specified by UnknownBits
// could be set on input to the CTLZ node. If this bit is set, the SRL
// will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
@ -7162,7 +7162,7 @@ static bool isTruncateOf(SelectionDAG &DAG, SDValue N, SDValue &Op,
DAG.computeKnownBits(Op, KnownZero, KnownOne);
if (!(KnownZero | APInt(Op.getValueSizeInBits(), 1)).isAllOnesValue())
if (!(KnownZero | 1).isAllOnesValue())
return false;
return true;
@ -7196,7 +7196,7 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
N0.getValueSizeInBits(),
std::min(Op.getValueSizeInBits(),
VT.getSizeInBits()));
if (TruncatedBits == (KnownZero & TruncatedBits)) {
if (TruncatedBits.isSubsetOf(KnownZero)) {
if (VT.bitsGT(Op.getValueType()))
return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, Op);
if (VT.bitsLT(Op.getValueType()))

2
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
View File

@ -1563,7 +1563,7 @@ ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
// If we know that all of the high bits of the shift amount are zero, then we
// can do this as a couple of simple shifts.
if ((KnownZero & HighBitMask) == HighBitMask) {
if (HighBitMask.isSubsetOf(KnownZero)) {
// Calculate 31-x. 31 is used instead of 32 to avoid creating an undefined
// shift if x is zero. We can use XOR here because x is known to be smaller
// than 32.

14
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -1969,7 +1969,7 @@ bool SelectionDAG::MaskedValueIsZero(SDValue Op, const APInt &Mask,
unsigned Depth) const {
APInt KnownZero, KnownOne;
computeKnownBits(Op, KnownZero, KnownOne, Depth);
return (KnownZero & Mask) == Mask;
return Mask.isSubsetOf(KnownZero);
}
/// If a SHL/SRA/SRL node has a constant or splat constant shift amount that
@ -2026,7 +2026,7 @@ void SelectionDAG::computeKnownBits(SDValue Op, APInt &KnownZero,
// Collect the known bits that are shared by every demanded vector element.
assert(NumElts == Op.getValueType().getVectorNumElements() &&
"Unexpected vector size");
KnownZero = KnownOne = APInt::getAllOnesValue(BitWidth);
KnownZero.setAllBits(); KnownOne.setAllBits();
for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i) {
if (!DemandedElts[i])
continue;
@ -2055,7 +2055,7 @@ void SelectionDAG::computeKnownBits(SDValue Op, APInt &KnownZero,
// Collect the known bits that are shared by every vector element referenced
// by the shuffle.
APInt DemandedLHS(NumElts, 0), DemandedRHS(NumElts, 0);
KnownZero = KnownOne = APInt::getAllOnesValue(BitWidth);
KnownZero.setAllBits(); KnownOne.setAllBits();
const ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op);
assert(NumElts == SVN->getMask().size() && "Unexpected vector size");
for (unsigned i = 0; i != NumElts; ++i) {
@ -2098,7 +2098,7 @@ void SelectionDAG::computeKnownBits(SDValue Op, APInt &KnownZero,
}
case ISD::CONCAT_VECTORS: {
// Split DemandedElts and test each of the demanded subvectors.
KnownZero = KnownOne = APInt::getAllOnesValue(BitWidth);
KnownZero.setAllBits(); KnownOne.setAllBits();
EVT SubVectorVT = Op.getOperand(0).getValueType();
unsigned NumSubVectorElts = SubVectorVT.getVectorNumElements();
unsigned NumSubVectors = Op.getNumOperands();
@ -2189,7 +2189,7 @@ void SelectionDAG::computeKnownBits(SDValue Op, APInt &KnownZero,
computeKnownBits(N0, KnownZero2, KnownOne2, SubDemandedElts, Depth + 1);
KnownZero = KnownOne = APInt::getAllOnesValue(BitWidth);
KnownZero.setAllBits(); KnownOne.setAllBits();
for (unsigned i = 0; i != NumElts; ++i)
if (DemandedElts[i]) {
unsigned Offset = (i % SubScale) * BitWidth;
@ -3073,7 +3073,7 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
// If the input is known to be 0 or 1, the output is 0/-1, which is all
// sign bits set.
if ((KnownZero | APInt(VTBits, 1)).isAllOnesValue())
if ((KnownZero | 1).isAllOnesValue())
return VTBits;
// If we are subtracting one from a positive number, there is no carry
@ -3097,7 +3097,7 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
computeKnownBits(Op.getOperand(1), KnownZero, KnownOne, Depth+1);
// If the input is known to be 0 or 1, the output is 0/-1, which is all
// sign bits set.
if ((KnownZero | APInt(VTBits, 1)).isAllOnesValue())
if ((KnownZero | 1).isAllOnesValue())
return VTBits;
// If the input is known to be positive (the sign bit is known clear),

2
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -1934,7 +1934,7 @@ bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
CurDAG->computeKnownBits(LHS, KnownZero, KnownOne);
// If all the missing bits in the or are already known to be set, match!
if ((NeededMask & KnownOne) == NeededMask)
if (NeededMask.isSubsetOf(KnownOne))
return true;
// TODO: check to see if missing bits are just not demanded.

43
lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@ -550,7 +550,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
return false; // Don't fall through, will infinitely loop.
case ISD::BUILD_VECTOR:
// Collect the known bits that are shared by every constant vector element.
KnownZero = KnownOne = APInt::getAllOnesValue(BitWidth);
KnownZero.setAllBits(); KnownOne.setAllBits();
for (SDValue SrcOp : Op->ops()) {
if (!isa<ConstantSDNode>(SrcOp)) {
// We can only handle all constant values - bail out with no known bits.
@ -618,12 +618,12 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
// If all of the demanded bits are known one on one side, return the other.
// These bits cannot contribute to the result of the 'and'.
if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
if (NewMask.isSubsetOf(KnownZero2 | KnownOne))
return TLO.CombineTo(Op, Op.getOperand(0));
if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
if (NewMask.isSubsetOf(KnownZero | KnownOne2))
return TLO.CombineTo(Op, Op.getOperand(1));
// If all of the demanded bits in the inputs are known zeros, return zero.
if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
if (NewMask.isSubsetOf(KnownZero | KnownZero2))
return TLO.CombineTo(Op, TLO.DAG.getConstant(0, dl, Op.getValueType()));
// If the RHS is a constant, see if we can simplify it.
if (ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask, TLO))
@ -649,15 +649,9 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
// If all of the demanded bits are known zero on one side, return the other.
// These bits cannot contribute to the result of the 'or'.
if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
if (NewMask.isSubsetOf(KnownOne2 | KnownZero))
return TLO.CombineTo(Op, Op.getOperand(0));
if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
return TLO.CombineTo(Op, Op.getOperand(1));
// If all of the potentially set bits on one side are known to be set on
// the other side, just use the 'other' side.
if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
return TLO.CombineTo(Op, Op.getOperand(0));
if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
if (NewMask.isSubsetOf(KnownOne | KnownZero2))
return TLO.CombineTo(Op, Op.getOperand(1));
// If the RHS is a constant, see if we can simplify it.
if (ShrinkDemandedConstant(Op, NewMask, TLO))
@ -683,9 +677,9 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
// If all of the demanded bits are known zero on one side, return the other.
// These bits cannot contribute to the result of the 'xor'.
if ((KnownZero & NewMask) == NewMask)
if (NewMask.isSubsetOf(KnownZero))
return TLO.CombineTo(Op, Op.getOperand(0));
if ((KnownZero2 & NewMask) == NewMask)
if (NewMask.isSubsetOf(KnownZero2))
return TLO.CombineTo(Op, Op.getOperand(1));
// If the operation can be done in a smaller type, do so.
if (ShrinkDemandedOp(Op, BitWidth, NewMask, TLO))
@ -709,7 +703,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
// into an AND, as we know the bits will be cleared.
// e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
// NB: it is okay if more bits are known than are requested
if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known on one side
if (NewMask.isSubsetOf(KnownZero|KnownOne)) { // all known on one side
if (KnownOne == KnownOne2) { // set bits are the same on both sides
EVT VT = Op.getValueType();
SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, dl, VT);
@ -968,9 +962,8 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
// If any of the demanded bits are produced by the sign extension, we also
// demand the input sign bit.
APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
if (HighBits.intersects(NewMask))
InDemandedMask |= APInt::getSignMask(VT.getScalarSizeInBits());
if (NewMask.countLeadingZeros() < ShAmt)
InDemandedMask.setSignBit();
if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
KnownZero, KnownOne, TLO, Depth+1))
@ -979,12 +972,10 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
KnownZero.lshrInPlace(ShAmt);
KnownOne.lshrInPlace(ShAmt);
// Handle the sign bit, adjusted to where it is now in the mask.
APInt SignMask = APInt::getSignMask(BitWidth).lshr(ShAmt);
// If the input sign bit is known to be zero, or if none of the top bits
// are demanded, turn this into an unsigned shift right.
if (KnownZero.intersects(SignMask) || (HighBits & ~NewMask) == HighBits) {
if (KnownZero[BitWidth - ShAmt - 1] ||
NewMask.countLeadingZeros() >= ShAmt) {
SDNodeFlags Flags;
Flags.setExact(cast<BinaryWithFlagsSDNode>(Op)->Flags.hasExact());
return TLO.CombineTo(Op,
@ -1002,9 +993,9 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
Op.getOperand(0), NewSA));
}
if (KnownOne.intersects(SignMask))
if (KnownOne[BitWidth - ShAmt - 1])
// New bits are known one.
KnownOne |= HighBits;
KnownOne.setHighBits(ShAmt);
}
break;
case ISD::SIGN_EXTEND_INREG: {
@ -1315,7 +1306,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
// If we know the value of all of the demanded bits, return this as a
// constant.
if ((NewMask & (KnownZero|KnownOne)) == NewMask) {
if (NewMask.isSubsetOf(KnownZero|KnownOne)) {
// Avoid folding to a constant if any OpaqueConstant is involved.
const SDNode *N = Op.getNode();
for (SDNodeIterator I = SDNodeIterator::begin(N),
@ -1346,7 +1337,7 @@ void TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
Op.getOpcode() == ISD::INTRINSIC_VOID) &&
"Should use MaskedValueIsZero if you don't know whether Op"
" is a target node!");
KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0);
KnownZero.clearAllBits(); KnownOne.clearAllBits();
}
/// This method can be implemented by targets that want to expose additional

2
lib/Target/X86/X86ISelLowering.cpp
View File

@ -26712,7 +26712,7 @@ void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
case X86ISD::VSRLI: {
if (auto *ShiftImm = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
if (ShiftImm->getAPIntValue().uge(VT.getScalarSizeInBits())) {
KnownZero = APInt::getAllOnesValue(BitWidth);
KnownZero.setAllBits();
break;
}