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Rename ARM "lane_cst" operands to "nohash_imm" since they are used for
several things other than Neon vector lane numbers. For inline assembly operands with a "c" print code, check that they really are immediates. llvm-svn: 79676
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@ -327,8 +327,8 @@ def addrmodepc : Operand<i32>,
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let MIOperandInfo = (ops GPR, i32imm);
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}
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def lane_cst : Operand<i32> {
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let PrintMethod = "printLaneOperand";
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def nohash_imm : Operand<i32> {
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let PrintMethod = "printNoHashImmediate";
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}
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//===----------------------------------------------------------------------===//
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@ -581,7 +581,7 @@ def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p),
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[]>;
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def LEApcrelJT : AXI1<0x0, (outs GPR:$dst),
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(ins i32imm:$label, lane_cst:$id, pred:$p),
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(ins i32imm:$label, nohash_imm:$id, pred:$p),
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Pseudo, IIC_iALUi,
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!strconcat(!strconcat(".set ${:private}PCRELV${:uid}, "
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"(${label}_${id}-(",
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@ -1658,27 +1658,27 @@ def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst),
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// VMOV : Vector Get Lane (move scalar to ARM core register)
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def VGETLNs8 : NVGetLane<0b11100101, 0b1011, 0b00,
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(outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
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(outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
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NoItinerary, "vmov", ".s8\t$dst, $src[$lane]",
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[(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src),
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imm:$lane))]>;
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def VGETLNs16 : NVGetLane<0b11100001, 0b1011, 0b01,
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(outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
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(outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
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NoItinerary, "vmov", ".s16\t$dst, $src[$lane]",
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[(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src),
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imm:$lane))]>;
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def VGETLNu8 : NVGetLane<0b11101101, 0b1011, 0b00,
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(outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
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(outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
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NoItinerary, "vmov", ".u8\t$dst, $src[$lane]",
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[(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src),
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imm:$lane))]>;
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def VGETLNu16 : NVGetLane<0b11101001, 0b1011, 0b01,
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(outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
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(outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
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NoItinerary, "vmov", ".u16\t$dst, $src[$lane]",
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[(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src),
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imm:$lane))]>;
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def VGETLNi32 : NVGetLane<0b11100001, 0b1011, 0b00,
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(outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
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(outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
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NoItinerary, "vmov", ".32\t$dst, $src[$lane]",
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[(set GPR:$dst, (extractelt (v2i32 DPR:$src),
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imm:$lane))]>;
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@ -1715,17 +1715,17 @@ def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
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let Constraints = "$src1 = $dst" in {
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def VSETLNi8 : NVSetLane<0b11100100, 0b1011, 0b00, (outs DPR:$dst),
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(ins DPR:$src1, GPR:$src2, lane_cst:$lane),
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(ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
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NoItinerary, "vmov", ".8\t$dst[$lane], $src2",
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[(set DPR:$dst, (vector_insert (v8i8 DPR:$src1),
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GPR:$src2, imm:$lane))]>;
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def VSETLNi16 : NVSetLane<0b11100000, 0b1011, 0b01, (outs DPR:$dst),
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(ins DPR:$src1, GPR:$src2, lane_cst:$lane),
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(ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
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NoItinerary, "vmov", ".16\t$dst[$lane], $src2",
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[(set DPR:$dst, (vector_insert (v4i16 DPR:$src1),
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GPR:$src2, imm:$lane))]>;
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def VSETLNi32 : NVSetLane<0b11100000, 0b1011, 0b00, (outs DPR:$dst),
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(ins DPR:$src1, GPR:$src2, lane_cst:$lane),
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(ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
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NoItinerary, "vmov", ".32\t$dst[$lane], $src2",
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[(set DPR:$dst, (insertelt (v2i32 DPR:$src1),
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GPR:$src2, imm:$lane))]>;
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@ -1788,14 +1788,14 @@ def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
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class VDUPLND<bits<2> op19_18, bits<2> op17_16, string OpcodeStr, ValueType Ty>
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: N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 0, 0,
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(outs DPR:$dst), (ins DPR:$src, lane_cst:$lane), NoItinerary,
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(outs DPR:$dst), (ins DPR:$src, nohash_imm:$lane), NoItinerary,
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!strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
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[(set DPR:$dst, (Ty (NEONvduplane (Ty DPR:$src), imm:$lane)))]>;
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class VDUPLNQ<bits<2> op19_18, bits<2> op17_16, string OpcodeStr,
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ValueType ResTy, ValueType OpTy>
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: N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 1, 0,
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(outs QPR:$dst), (ins DPR:$src, lane_cst:$lane), NoItinerary,
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(outs QPR:$dst), (ins DPR:$src, nohash_imm:$lane), NoItinerary,
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!strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
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[(set QPR:$dst, (ResTy (NEONvduplane (OpTy DPR:$src), imm:$lane)))]>;
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@ -632,7 +632,7 @@ def tLEApcrel : T1I<(outs tGPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi,
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"adr$p $dst, #$label", []>;
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def tLEApcrelJT : T1I<(outs tGPR:$dst),
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(ins i32imm:$label, lane_cst:$id, pred:$p),
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(ins i32imm:$label, nohash_imm:$id, pred:$p),
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IIC_iALUi, "adr$p $dst, #${label}_${id}", []>;
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//===----------------------------------------------------------------------===//
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@ -431,7 +431,7 @@ def t2LEApcrel : T2XI<(outs GPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi,
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"adr$p.w $dst, #$label", []>;
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def t2LEApcrelJT : T2XI<(outs GPR:$dst),
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(ins i32imm:$label, lane_cst:$id, pred:$p), IIC_iALUi,
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(ins i32imm:$label, nohash_imm:$id, pred:$p), IIC_iALUi,
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"adr$p.w $dst, #${label}_${id}", []>;
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// ADD r, sp, {so_imm|i12}
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@ -164,7 +164,7 @@ namespace {
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void printJTBlockOperand(const MachineInstr *MI, int OpNum);
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void printJT2BlockOperand(const MachineInstr *MI, int OpNum);
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void printTBAddrMode(const MachineInstr *MI, int OpNum);
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void printLaneOperand(const MachineInstr *MI, int OpNum);
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void printNoHashImmediate(const MachineInstr *MI, int OpNum);
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virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
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unsigned AsmVariant, const char *ExtraCode);
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@ -1010,7 +1010,7 @@ void ARMAsmPrinter::printTBAddrMode(const MachineInstr *MI, int OpNum) {
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O << ']';
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}
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void ARMAsmPrinter::printLaneOperand(const MachineInstr *MI, int OpNum) {
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void ARMAsmPrinter::printNoHashImmediate(const MachineInstr *MI, int OpNum) {
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O << MI->getOperand(OpNum).getImm();
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}
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@ -1029,7 +1029,9 @@ bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
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}
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// Fallthrough
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case 'c': // Don't print "#" before an immediate operand.
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printLaneOperand(MI, OpNum);
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if (!MI->getOperand(OpNum).isImm())
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return true;
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printNoHashImmediate(MI, OpNum);
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return false;
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case 'P': // Print a VFP double precision register.
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printOperand(MI, OpNum);
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