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[mips] Support the "o" inline asm constraint

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As well as other LLVM targets we do not handle "offsettable"
memory addresses in any special way. In other words, the "o" constraint
is an exact equivalent of the "m" one. But some existing code require
the "o" constraint support.

This fixes PR42589.

Differential Revision: https://reviews.llvm.org/D64792

llvm-svn: 366299
This commit is contained in:
Simon Atanasyan 2019-07-17 08:11:15 +00:00
parent 00cc875c77
commit 94c2670118
3 changed files with 64 additions and 0 deletions
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2
lib/Target/Mips/MipsISelLowering.h
View File

@ -653,6 +653,8 @@ class TargetRegisterClass;
unsigned unsigned
getInlineAsmMemConstraint(StringRef ConstraintCode) const override { getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
if (ConstraintCode == "o")
return InlineAsm::Constraint_o;
if (ConstraintCode == "R") if (ConstraintCode == "R")
return InlineAsm::Constraint_R; return InlineAsm::Constraint_R;
if (ConstraintCode == "ZC") if (ConstraintCode == "ZC")

1
lib/Target/Mips/MipsSEISelDAGToDAG.cpp
View File

@ -1237,6 +1237,7 @@ SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32)); OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
return false; return false;
case InlineAsm::Constraint_m: case InlineAsm::Constraint_m:
case InlineAsm::Constraint_o:
if (selectAddrRegImm16(Op, Base, Offset)) { if (selectAddrRegImm16(Op, Base, Offset)) {
OutOps.push_back(Base); OutOps.push_back(Base);
OutOps.push_back(Offset); OutOps.push_back(Offset);

61
test/CodeGen/Mips/inlineasm_constraint_o.ll Normal file
View File

@ -0,0 +1,61 @@
; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s
@data = global [8193 x i32] zeroinitializer
define void @o(i32 *%p) nounwind {
entry:
; CHECK-LABEL: o:
call void asm sideeffect "lw $$1, $0", "*o,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 0))
; CHECK: lw $[[BASEPTR:[0-9]+]], %got(data)(
; CHECK: #APP
; CHECK: lw $1, 0($[[BASEPTR]])
; CHECK: #NO_APP
ret void
}
define void @o_offset_4(i32 *%p) nounwind {
entry:
; CHECK-LABEL: o_offset_4:
call void asm sideeffect "lw $$1, $0", "*o,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 1))
; CHECK: lw $[[BASEPTR:[0-9]+]], %got(data)(
; CHECK: #APP
; CHECK: lw $1, 4($[[BASEPTR]])
; CHECK: #NO_APP
ret void
}
define void @o_offset_32764(i32 *%p) nounwind {
entry:
; CHECK-LABEL: o_offset_32764:
call void asm sideeffect "lw $$1, $0", "*o,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 8191))
; CHECK-DAG: lw $[[BASEPTR:[0-9]+]], %got(data)(
; CHECK: #APP
; CHECK: lw $1, 32764($[[BASEPTR]])
; CHECK: #NO_APP
ret void
}
define void @o_offset_32768(i32 *%p) nounwind {
entry:
; CHECK-LABEL: o_offset_32768:
call void asm sideeffect "lw $$1, $0", "*o,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 8192))
; CHECK-DAG: lw $[[BASEPTR:[0-9]+]], %got(data)(
; CHECK-DAG: ori $[[T0:[0-9]+]], $zero, 32768
; CHECK: addu $[[BASEPTR2:[0-9]+]], $[[BASEPTR]], $[[T0]]
; CHECK: #APP
; CHECK: lw $1, 0($[[BASEPTR2]])
; CHECK: #NO_APP
ret void
}