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modified printing of debug messages

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llvm-svn: 593
This commit is contained in:
Ruchira Sasanka 2001-09-15 19:11:31 +00:00
parent ecc5b3b882
commit 9517b55411
3 changed files with 4 additions and 117 deletions
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27
lib/Target/Sparc/Sparc.cpp
View File

@ -90,32 +90,7 @@ UltraSparcSchedInfo::initializeResources()
//---------------------------------------------------------------------------
// class UltraSparcRegInfo
//
// Purpose:
// This class provides info about sparc register classes.
//--------------------------------------------------------------------------
#if 0
UltraSparcRegInfo::UltraSparcRegInfo(const UltraSparc *const USI ) :
UltraSparcInfo(USI),
NumOfIntArgRegs(6),
NumOfFloatArgRegs(6)
{
MachineRegClassArr.push_back( new SparcIntRegClass(IntRegClassID) );
MachineRegClassArr.push_back( new SparcFloatRegClass(FloatRegClassID) );
MachineRegClassArr.push_back( new SparcIntCCRegClass(IntCCRegClassID) );
MachineRegClassArr.push_back( new SparcFloatCCRegClass(FloatCCRegClassID));
assert( SparcFloatRegOrder::StartOfNonVolatileRegs == 6 &&
"6 Float regs are used for float arg passing");
}
// ***** TODO insert deletes for reg classes
UltraSparcRegInfo::~UltraSparcRegInfo(void) { } // empty destructor
#endif
//---------------------------------------------------------------------------
// UltraSparcRegInfo
@ -427,7 +402,7 @@ UltraSparc::UltraSparc() : TargetMachine("UltraSparc-Native"),
optSizeForSubWordData = 4;
minMemOpWordSize = 8;
maxAtomicMemOpWordSize = 8;
zeroRegNum = 0; // %g0 always gives 0 on Sparc
zeroRegNum = RegInfo.getZeroReg(); // %g0 always gives 0 on Sparc
}

16
lib/Target/Sparc/SparcInternals.h
View File

@ -945,22 +945,12 @@ class UltraSparcRegInfo : public MachineRegInfo
return res;
}
#if 0
unsigned getRCIDOfMachineOp (const MachineOperand & Op) const {
unsigned Type = getRegClassIDOfValue( Op.getVRegValue() );
if( Op.getOperandType() == MachineOperand::MO_CCRegister )
return Type + 2; // because of the order of CC classes
else return Type;
// returns the register tha contains always zero
inline unsigned getZeroReg() {
return SparcIntRegOrder::g0;
}
#endif
void colorArgs(const Method *const Meth, LiveRangeInfo& LRI) const;
static void printReg(const LiveRange *const LR) ;

78
lib/Target/Sparc/SparcRegInfo.cpp
View File

@ -237,81 +237,3 @@ void SparcFloatRegClass::colorIGNode(IGNode * Node,bool IsColorUsedArr[]) const
#if 0
//-----------------------------------------------------------------------------
// Float Register Class
//-----------------------------------------------------------------------------
void SparcFloatRegClass::colorIGNode(IGNode * Node,bool IsColorUsedArr[]) const
{
/* Algorithm:
Record the color of all neighbors.
Single precision can use f0 - f31
Double precision can use f0 - f63
if LR is a double, try to allocate f32 - f63.
if the above attempt fails, or Value is single presion, try to allcoate
f0 - f31.
*/
unsigned NumNeighbors = Node->getNumOfNeighbors(); // total # of neighbors
for(unsigned n=0; n < NumNeighbors; n++) { // for each neigh
IGNode *NeighIGNode = Node->getAdjIGNode(n);
if( NeighIGNode->hasColor() ) { // if neigh has a color
IsColorUsedArr[ NeighIGNode->getColor() ] = true; // record that color
if( NeighIGNode->getTypeID() == Type::DoubleTyID )
IsColorUsedArr[ (NeighIGNode->getColor()) + 1 ] = true;
}
}
unsigned SearchStart; // start pos of color in pref-order
bool ColorFound= false; // have we found a color yet?
unsigned c;
if( Node->getTypeID() == Type::DoubleTyID ) { // if value is a double
// search the double only reigon (f32 - f63)
for( c=32; c < 64; c+= 2) {
if( ! IsColorUsedArr[ c ] ) { ColorFound = true; break; }
}
// search f0 - f31 region
if( ! ColorFound ) { // if color not found
for( c=0; c < 32; c+= 2) {
if( ! IsColorUsedArr[ c ] ) { ColorFound = true; break; }
}
}
}
else { // value is Single
for( c=0; c < 32; c++) {
if( ! IsColorUsedArr[ c ] ) { ColorFound = true; break; }
}
}
if( ColorFound)
Node->setColor(c); // first color found in preferred order
else
Node->markForSpill(); // no color found - must spill
if( DEBUG_RA)
UltraSparcRegInfo::printReg( Node->getParentLR() );
}
#endif