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https://github.com/RPCS3/llvm-mirror.git
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Add FMF management to common fp intrinsics in GlobalIsel
Summary: This the initial code change to facilitate managing FMF flags from Instructions to MI wrt Intrinsics in Global Isel. Eventually the GlobalObserver interface will be added as well, where FMF additions can be tracked for the builder and CSE. Reviewers: aditya_nandakumar, bogner Reviewed By: bogner Subscribers: rovka, kristof.beyls, javed.absar Differential Revision: https://reviews.llvm.org/D55668 llvm-svn: 349514
This commit is contained in:
Michael Berg
parent
776f1841f2
commit
951bbe1a31
@ -354,8 +354,10 @@ bool IRTranslator::translateCompare(const User &U,
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else if (Pred == CmpInst::FCMP_TRUE)
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MIRBuilder.buildCopy(
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Res, getOrCreateVReg(*Constant::getAllOnesValue(CI->getType())));
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else
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MIRBuilder.buildFCmp(Pred, Res, Op0, Op1);
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else {
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auto FCmp = MIRBuilder.buildFCmp(Pred, Res, Op0, Op1);
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FCmp->copyIRFlags(*CI);
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}
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return true;
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}
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@ -588,8 +590,15 @@ bool IRTranslator::translateSelect(const User &U,
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ArrayRef<unsigned> Op0Regs = getOrCreateVRegs(*U.getOperand(1));
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ArrayRef<unsigned> Op1Regs = getOrCreateVRegs(*U.getOperand(2));
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for (unsigned i = 0; i < ResRegs.size(); ++i)
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MIRBuilder.buildSelect(ResRegs[i], Tst, Op0Regs[i], Op1Regs[i]);
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const SelectInst &SI = cast<SelectInst>(U);
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const CmpInst *Cmp = dyn_cast<CmpInst>(SI.getCondition());
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for (unsigned i = 0; i < ResRegs.size(); ++i) {
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auto Select =
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MIRBuilder.buildSelect(ResRegs[i], Tst, Op0Regs[i], Op1Regs[i]);
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if (Cmp && isa<FPMathOperator>(Cmp)) {
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Select->copyIRFlags(*Cmp);
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}
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}
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return true;
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}
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@ -869,42 +878,56 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
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return translateOverflowIntrinsic(CI, TargetOpcode::G_UMULO, MIRBuilder);
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case Intrinsic::smul_with_overflow:
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return translateOverflowIntrinsic(CI, TargetOpcode::G_SMULO, MIRBuilder);
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case Intrinsic::pow:
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MIRBuilder.buildInstr(TargetOpcode::G_FPOW)
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case Intrinsic::pow: {
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auto Pow = MIRBuilder.buildInstr(TargetOpcode::G_FPOW)
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.addDef(getOrCreateVReg(CI))
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.addUse(getOrCreateVReg(*CI.getArgOperand(0)))
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.addUse(getOrCreateVReg(*CI.getArgOperand(1)));
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Pow->copyIRFlags(CI);
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return true;
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case Intrinsic::exp:
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MIRBuilder.buildInstr(TargetOpcode::G_FEXP)
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}
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case Intrinsic::exp: {
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auto Exp = MIRBuilder.buildInstr(TargetOpcode::G_FEXP)
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.addDef(getOrCreateVReg(CI))
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.addUse(getOrCreateVReg(*CI.getArgOperand(0)));
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Exp->copyIRFlags(CI);
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return true;
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case Intrinsic::exp2:
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MIRBuilder.buildInstr(TargetOpcode::G_FEXP2)
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}
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case Intrinsic::exp2: {
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auto Exp2 = MIRBuilder.buildInstr(TargetOpcode::G_FEXP2)
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.addDef(getOrCreateVReg(CI))
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.addUse(getOrCreateVReg(*CI.getArgOperand(0)));
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Exp2->copyIRFlags(CI);
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return true;
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case Intrinsic::log:
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MIRBuilder.buildInstr(TargetOpcode::G_FLOG)
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}
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case Intrinsic::log: {
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auto Log = MIRBuilder.buildInstr(TargetOpcode::G_FLOG)
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.addDef(getOrCreateVReg(CI))
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.addUse(getOrCreateVReg(*CI.getArgOperand(0)));
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Log->copyIRFlags(CI);
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return true;
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case Intrinsic::log2:
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MIRBuilder.buildInstr(TargetOpcode::G_FLOG2)
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}
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case Intrinsic::log2: {
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auto Log2 = MIRBuilder.buildInstr(TargetOpcode::G_FLOG2)
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.addDef(getOrCreateVReg(CI))
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.addUse(getOrCreateVReg(*CI.getArgOperand(0)));
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Log2->copyIRFlags(CI);
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return true;
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case Intrinsic::log10:
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MIRBuilder.buildInstr(TargetOpcode::G_FLOG10)
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}
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case Intrinsic::log10: {
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auto Log10 = MIRBuilder.buildInstr(TargetOpcode::G_FLOG10)
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.addDef(getOrCreateVReg(CI))
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.addUse(getOrCreateVReg(*CI.getArgOperand(0)));
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Log10->copyIRFlags(CI);
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return true;
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case Intrinsic::fabs:
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MIRBuilder.buildInstr(TargetOpcode::G_FABS)
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}
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case Intrinsic::fabs: {
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auto Fabs = MIRBuilder.buildInstr(TargetOpcode::G_FABS)
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.addDef(getOrCreateVReg(CI))
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.addUse(getOrCreateVReg(*CI.getArgOperand(0)));
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Fabs->copyIRFlags(CI);
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return true;
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}
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case Intrinsic::trunc:
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MIRBuilder.buildInstr(TargetOpcode::G_INTRINSIC_TRUNC)
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.addDef(getOrCreateVReg(CI))
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@ -915,13 +938,15 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
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.addDef(getOrCreateVReg(CI))
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.addUse(getOrCreateVReg(*CI.getArgOperand(0)));
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return true;
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case Intrinsic::fma:
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MIRBuilder.buildInstr(TargetOpcode::G_FMA)
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case Intrinsic::fma: {
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auto FMA = MIRBuilder.buildInstr(TargetOpcode::G_FMA)
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.addDef(getOrCreateVReg(CI))
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.addUse(getOrCreateVReg(*CI.getArgOperand(0)))
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.addUse(getOrCreateVReg(*CI.getArgOperand(1)))
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.addUse(getOrCreateVReg(*CI.getArgOperand(2)));
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FMA->copyIRFlags(CI);
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return true;
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}
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case Intrinsic::fmuladd: {
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const TargetMachine &TM = MF->getTarget();
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const TargetLowering &TLI = *MF->getSubtarget().getTargetLowering();
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@ -933,11 +958,14 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
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TLI.isFMAFasterThanFMulAndFAdd(TLI.getValueType(*DL, CI.getType()))) {
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// TODO: Revisit this to see if we should move this part of the
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// lowering to the combiner.
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MIRBuilder.buildInstr(TargetOpcode::G_FMA, {Dst}, {Op0, Op1, Op2});
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auto FMA = MIRBuilder.buildInstr(TargetOpcode::G_FMA, {Dst}, {Op0, Op1, Op2});
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FMA->copyIRFlags(CI);
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} else {
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LLT Ty = getLLTForType(*CI.getType(), *DL);
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auto FMul = MIRBuilder.buildInstr(TargetOpcode::G_FMUL, {Ty}, {Op0, Op1});
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MIRBuilder.buildInstr(TargetOpcode::G_FADD, {Dst}, {FMul, Op2});
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FMul->copyIRFlags(CI);
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auto FAdd = MIRBuilder.buildInstr(TargetOpcode::G_FADD, {Dst}, {FMul, Op2});
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FAdd->copyIRFlags(CI);
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}
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return true;
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}
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@ -1173,12 +1173,12 @@ define void @test_constant_float(float* %addr) {
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; CHECK: [[BOOLADDR:%[0-9]+]]:_(p0) = COPY $x2
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; CHECK: [[LHS:%[0-9]+]]:_(s32) = G_LOAD [[LHSADDR]](p0)
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; CHECK: [[RHS:%[0-9]+]]:_(s32) = G_LOAD [[RHSADDR]](p0)
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; CHECK: [[TST:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[LHS]](s32), [[RHS]]
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; CHECK: [[TST:%[0-9]+]]:_(s1) = nnan ninf nsz arcp contract afn reassoc G_FCMP floatpred(oge), [[LHS]](s32), [[RHS]]
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; CHECK: G_STORE [[TST]](s1), [[BOOLADDR]](p0)
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define void @float_comparison(float* %a.addr, float* %b.addr, i1* %bool.addr) {
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%a = load float, float* %a.addr
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%b = load float, float* %b.addr
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%res = fcmp oge float %a, %b
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%res = fcmp nnan ninf nsz arcp contract afn reassoc oge float %a, %b
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store i1 %res, i1* %bool.addr
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ret void
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}
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@ -1338,9 +1338,9 @@ define float @test_pow_intrin(float %l, float %r) {
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; CHECK-LABEL: name: test_pow_intrin
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; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY $s1
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; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FPOW [[LHS]], [[RHS]]
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; CHECK: [[RES:%[0-9]+]]:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FPOW [[LHS]], [[RHS]]
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; CHECK: $s0 = COPY [[RES]]
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%res = call float @llvm.pow.f32(float %l, float %r)
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%res = call nnan ninf nsz arcp contract afn reassoc float @llvm.pow.f32(float %l, float %r)
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ret float %res
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}
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@ -1350,9 +1350,9 @@ define float @test_fma_intrin(float %a, float %b, float %c) {
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; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK: [[B:%[0-9]+]]:_(s32) = COPY $s1
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; CHECK: [[C:%[0-9]+]]:_(s32) = COPY $s2
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; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FMA [[A]], [[B]], [[C]]
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; CHECK: [[RES:%[0-9]+]]:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FMA [[A]], [[B]], [[C]]
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; CHECK: $s0 = COPY [[RES]]
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%res = call float @llvm.fma.f32(float %a, float %b, float %c)
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%res = call nnan ninf nsz arcp contract afn reassoc float @llvm.fma.f32(float %a, float %b, float %c)
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ret float %res
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}
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@ -1360,9 +1360,9 @@ declare float @llvm.exp.f32(float)
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define float @test_exp_intrin(float %a) {
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; CHECK-LABEL: name: test_exp_intrin
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; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FEXP [[A]]
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; CHECK: [[RES:%[0-9]+]]:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FEXP [[A]]
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; CHECK: $s0 = COPY [[RES]]
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%res = call float @llvm.exp.f32(float %a)
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%res = call nnan ninf nsz arcp contract afn reassoc float @llvm.exp.f32(float %a)
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ret float %res
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}
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@ -1370,9 +1370,9 @@ declare float @llvm.exp2.f32(float)
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define float @test_exp2_intrin(float %a) {
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; CHECK-LABEL: name: test_exp2_intrin
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; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FEXP2 [[A]]
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; CHECK: [[RES:%[0-9]+]]:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FEXP2 [[A]]
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; CHECK: $s0 = COPY [[RES]]
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%res = call float @llvm.exp2.f32(float %a)
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%res = call nnan ninf nsz arcp contract afn reassoc float @llvm.exp2.f32(float %a)
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ret float %res
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}
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@ -1380,9 +1380,9 @@ declare float @llvm.log.f32(float)
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define float @test_log_intrin(float %a) {
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; CHECK-LABEL: name: test_log_intrin
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; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FLOG [[A]]
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; CHECK: [[RES:%[0-9]+]]:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FLOG [[A]]
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; CHECK: $s0 = COPY [[RES]]
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%res = call float @llvm.log.f32(float %a)
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%res = call nnan ninf nsz arcp contract afn reassoc float @llvm.log.f32(float %a)
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ret float %res
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}
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@ -1400,9 +1400,9 @@ declare float @llvm.log10.f32(float)
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define float @test_log10_intrin(float %a) {
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; CHECK-LABEL: name: test_log10_intrin
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; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FLOG10 [[A]]
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; CHECK: [[RES:%[0-9]+]]:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FLOG10 [[A]]
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; CHECK: $s0 = COPY [[RES]]
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%res = call float @llvm.log10.f32(float %a)
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%res = call nnan ninf nsz arcp contract afn reassoc float @llvm.log10.f32(float %a)
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ret float %res
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}
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@ -1410,9 +1410,9 @@ declare float @llvm.fabs.f32(float)
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define float @test_fabs_intrin(float %a) {
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; CHECK-LABEL: name: test_fabs_intrin
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; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FABS [[A]]
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; CHECK: [[RES:%[0-9]+]]:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FABS [[A]]
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; CHECK: $s0 = COPY [[RES]]
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%res = call float @llvm.fabs.f32(float %a)
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%res = call nnan ninf nsz arcp contract afn reassoc float @llvm.fabs.f32(float %a)
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ret float %res
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}
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