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Emit COPY instead of FMR/FMSD instructions for floating point conversion on
PowerPC. llvm-svn: 108555
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663dd0eb36
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@ -80,7 +80,7 @@ bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
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destReg = MI.getOperand(0).getReg();
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return true;
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}
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} else if (oc == PPC::FMR || oc == PPC::FMRSD) { // fmr r1, r2
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} else if (oc == PPC::FMR) { // fmr r1, r2
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assert(MI.getNumOperands() >= 2 &&
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MI.getOperand(0).isReg() &&
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MI.getOperand(1).isReg() &&
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@ -1022,9 +1022,7 @@ let Uses = [RM] in {
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}
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}
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/// FMR is split into 2 versions, one for 4/8 byte FP, and one for extending.
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///
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/// Note that these are defined as pseudo-ops on the PPC970 because they are
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/// Note that FMR is defined as pseudo-ops on the PPC970 because they are
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/// often coalesced away and we don't want the dispatch group builder to think
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/// that they will fill slots (which could cause the load of a LSU reject to
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/// sneak into a d-group with a store).
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@ -1032,10 +1030,6 @@ def FMR : XForm_26<63, 72, (outs F4RC:$frD), (ins F4RC:$frB),
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"fmr $frD, $frB", FPGeneral,
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[]>, // (set F4RC:$frD, F4RC:$frB)
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PPC970_Unit_Pseudo;
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def FMRSD : XForm_26<63, 72, (outs F8RC:$frD), (ins F4RC:$frB),
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"fmr $frD, $frB", FPGeneral,
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[(set F8RC:$frD, (fextend F4RC:$frB))]>,
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PPC970_Unit_Pseudo;
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let PPC970_Unit = 3 in { // FPU Operations.
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// These are artificially split into two different forms, for 4/8 byte FP.
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@ -1476,10 +1470,13 @@ def : Pat<(extloadi16 iaddr:$src),
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(LHZ iaddr:$src)>;
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def : Pat<(extloadi16 xaddr:$src),
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(LHZX xaddr:$src)>;
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def : Pat<(extloadf32 iaddr:$src),
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(FMRSD (LFS iaddr:$src))>;
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def : Pat<(extloadf32 xaddr:$src),
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(FMRSD (LFSX xaddr:$src))>;
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def : Pat<(f64 (extloadf32 iaddr:$src)),
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(COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
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def : Pat<(f64 (extloadf32 xaddr:$src)),
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(COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
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def : Pat<(f64 (fextend F4RC:$src)),
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(COPY_TO_REGCLASS F4RC:$src, F8RC)>;
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// Memory barriers
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def : Pat<(membarrier (i32 imm /*ll*/),
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