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Part 1 of 3 patches that completes very long conditional branches
in constant islands for Mips16. We introdcuce JalB16 as a synomnym for Jal16. It makes it easier to read and is also necessary because Jal16 is a call instruction but JalB16 is being used as a branch. Various parts of LLVM will not work properly even in this late stage of the backend if we use what was declared as a call instruction to function as a branch. For one, basic block labels may not get emitted in some situations. llvm-svn: 195968
This commit is contained in:
Reed Kotler
parent
b8cffe14c6
commit
95269c69db
@ -120,6 +120,15 @@ class FJAL16_ins<bits<1> _X, string asmstr,
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itin> {
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let isCodeGenOnly=1;
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}
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class FJALB16_ins<bits<1> _X, string asmstr,
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InstrItinClass itin>:
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FJAL16<_X, (outs), (ins simm20:$imm),
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!strconcat(asmstr, "\t$imm\t# branch\n\tnop"),[],
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itin> {
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let isCodeGenOnly=1;
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}
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//
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// EXT-I instruction format
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//
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@ -737,6 +746,12 @@ def Jal16 : FJAL16_ins<0b0, "jal", IIAlu> {
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let Defs = [RA];
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}
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def JalB16 : FJALB16_ins<0b0, "jal", IIAlu>, branch16 {
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let hasDelaySlot = 0; // not true, but we add the nop for now
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let isBranch=1;
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let Defs = [RA];
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}
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//
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// Format: JR ra MIPS16e
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// Purpose: Jump Register Through Register ra
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@ -85,7 +85,7 @@ static unsigned int branchTargetOperand(MachineInstr *MI) {
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case Mips::BteqzX16:
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case Mips::Btnez16:
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case Mips::BtnezX16:
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case Mips::Jal16:
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case Mips::JalB16:
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return 0;
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case Mips::BeqzRxImm16:
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case Mips::BeqzRxImmX16:
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@ -96,6 +96,16 @@ static unsigned int branchTargetOperand(MachineInstr *MI) {
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llvm_unreachable("Unknown branch type");
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}
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static bool isUnconditionalBranch(unsigned int Opcode) {
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switch (Opcode) {
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default: return false;
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case Mips::Bimm16:
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case Mips::BimmX16:
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case Mips::JalB16:
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return true;
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}
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}
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static unsigned int longformBranchOpcode(unsigned int Opcode) {
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switch (Opcode) {
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case Mips::Bimm16:
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@ -107,8 +117,8 @@ static unsigned int longformBranchOpcode(unsigned int Opcode) {
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case Mips::Btnez16:
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case Mips::BtnezX16:
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return Mips::BtnezX16;
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case Mips::Jal16:
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return Mips::Jal16;
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case Mips::JalB16:
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return Mips::JalB16;
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case Mips::BeqzRxImm16:
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case Mips::BeqzRxImmX16:
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return Mips::BeqzRxImmX16;
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@ -1561,7 +1571,7 @@ MipsConstantIslands::fixupUnconditionalBr(ImmBranch &Br) {
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//
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DestBB->setAlignment(2);
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Br.MaxDisp = ((1<<24)-1) * 2;
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MI->setDesc(TII->get(Mips::Jal16));
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MI->setDesc(TII->get(Mips::JalB16));
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}
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BBInfo[MBB->getNumber()].Size += 2;
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adjustBBOffsetsAfter(MBB);
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@ -1592,17 +1602,14 @@ MipsConstantIslands::fixupConditionalBr(ImmBranch &Br) {
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MI->setDesc(TII->get(LongFormOpcode));
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return true;
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}
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llvm_unreachable("Fixup of very long conditional branch not working yet.");
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// Add an unconditional branch to the destination and invert the branch
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// condition to jump over it:
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// blt L1
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// bteqz L1
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// =>
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// bge L2
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// bnez L2
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// b L1
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// L2:
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unsigned CCReg = 0; // FIXME
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unsigned CC=0; //FIXME
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// If the branch is at the end of its MBB and that has a fall-through block,
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// direct the updated conditional branch to the fall-through block. Otherwise,
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@ -1611,28 +1618,34 @@ MipsConstantIslands::fixupConditionalBr(ImmBranch &Br) {
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MachineInstr *BMI = &MBB->back();
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bool NeedSplit = (BMI != MI) || !BBHasFallthrough(MBB);
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++NumCBrFixed;
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if (BMI != MI) {
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if (llvm::next(MachineBasicBlock::iterator(MI)) == prior(MBB->end()) &&
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BMI->getOpcode() == Br.UncondBr) {
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isUnconditionalBranch(BMI->getOpcode())) {
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// Last MI in the BB is an unconditional branch. Can we simply invert the
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// condition and swap destinations:
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// beq L1
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// beqz L1
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// b L2
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// =>
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// bne L2
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// bnez L2
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// b L1
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MachineBasicBlock *NewDest = BMI->getOperand(0).getMBB();
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unsigned BMITargetOperand = branchTargetOperand(BMI);
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MachineBasicBlock *NewDest =
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BMI->getOperand(BMITargetOperand).getMBB();
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if (isBBInRange(MI, NewDest, Br.MaxDisp)) {
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DEBUG(dbgs() << " Invert Bcc condition and swap its destination with "
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<< *BMI);
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BMI->getOperand(0).setMBB(DestBB);
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MI->getOperand(0).setMBB(NewDest);
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MI->setDesc(TII->get(TII->getOppositeBranchOpc(Opcode)));
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BMI->getOperand(BMITargetOperand).setMBB(DestBB);
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MI->getOperand(TargetOperand).setMBB(NewDest);
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return true;
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}
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}
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}
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llvm_unreachable("unsupported range of unconditional branch");
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if (NeedSplit) {
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splitBlockBeforeInstr(MI);
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// No need for the branch to the next block. We're adding an unconditional
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@ -1651,7 +1664,7 @@ MipsConstantIslands::fixupConditionalBr(ImmBranch &Br) {
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// Insert a new conditional branch and a new unconditional branch.
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// Also update the ImmBranch as well as adding a new entry for the new branch.
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BuildMI(MBB, DebugLoc(), TII->get(MI->getOpcode()))
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.addMBB(NextBB).addImm(CC).addReg(CCReg);
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.addMBB(NextBB);
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Br.MI = &MBB->back();
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BBInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(&MBB->back());
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BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB);
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59
test/CodeGen/Mips/lcb3c.ll
Normal file
59
test/CodeGen/Mips/lcb3c.ll
Normal file
@ -0,0 +1,59 @@
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; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=static -O0 < %s | FileCheck %s -check-prefix=lcb
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@i = global i32 0, align 4
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@j = common global i32 0, align 4
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@k = common global i32 0, align 4
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; Function Attrs: nounwind
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define i32 @s() #0 {
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entry:
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%0 = load i32* @i, align 4
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%cmp = icmp eq i32 %0, 0
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br i1 %cmp, label %if.then, label %if.else
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if.then: ; preds = %entry
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store i32 0, i32* @i, align 4
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call void asm sideeffect ".space 1000", ""() #1, !srcloc !1
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br label %if.end
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if.else: ; preds = %entry
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store i32 1, i32* @i, align 4
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br label %if.end
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if.end: ; preds = %if.else, %if.then
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ret i32 0
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; lcb: bnez $2, $BB0_2
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; lcb: b $BB0_1 # 16 bit inst
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; lcb: $BB0_1: # %if.then
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}
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; Function Attrs: nounwind
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define i32 @b() #0 {
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entry:
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%0 = load i32* @i, align 4
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%cmp = icmp eq i32 %0, 0
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br i1 %cmp, label %if.then, label %if.else
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if.then: ; preds = %entry
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store i32 0, i32* @i, align 4
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call void asm sideeffect ".space 1000000", ""() #1, !srcloc !2
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br label %if.end
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if.else: ; preds = %entry
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store i32 1, i32* @i, align 4
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br label %if.end
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if.end: ; preds = %if.else, %if.then
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ret i32 0
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}
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; lcb: beqz $2, $BB1_1 # 16 bit inst
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; lcb: jal $BB1_2 # branch
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; lcb: $BB1_1: # %if.then
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attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
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attributes #1 = { nounwind }
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!1 = metadata !{i32 65}
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!2 = metadata !{i32 167}
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