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[Test] Add more tests demonstrating oddities in behavior of LSR
These tests demonstrate that LSR does not insert IV increment into the latch block (as it supposes to) when it can use an existing Phi as IV rather than creating a new LSR IV.
This commit is contained in:
Max Kazantsev
parent
9912faec1f
commit
95717fc944
@ -2,8 +2,8 @@
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; RUN: llc < %s -mtriple=x86_64-apple-macosx | FileCheck %s
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; TODO: We can get rid of movq here by using different offset and %rax.
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define i32 @test(i32* %p, i64 %len, i32 %x) {
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; CHECK-LABEL: test:
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define i32 @test_01(i32* %p, i64 %len, i32 %x) {
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; CHECK-LABEL: test_01:
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; CHECK: ## %bb.0: ## %entry
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; CHECK-NEXT: movq %rsi, %rax
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; CHECK-NEXT: .p2align 4, 0x90
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@ -42,3 +42,89 @@ exit: ; preds = %loop
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failure: ; preds = %backedge
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unreachable
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}
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define i32 @test_02(i32* %p, i64 %len, i32 %x) {
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; CHECK-LABEL: test_02:
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; CHECK: ## %bb.0: ## %entry
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; CHECK-NEXT: .p2align 4, 0x90
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; CHECK-NEXT: LBB1_1: ## %loop
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; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: testq %rsi, %rsi
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; CHECK-NEXT: je LBB1_4
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; CHECK-NEXT: ## %bb.2: ## %backedge
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; CHECK-NEXT: ## in Loop: Header=BB1_1 Depth=1
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; CHECK-NEXT: cmpl %edx, -4(%rdi,%rsi,4)
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; CHECK-NEXT: leaq -1(%rsi), %rsi
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; CHECK-NEXT: jne LBB1_1
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; CHECK-NEXT: ## %bb.3: ## %failure
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; CHECK-NEXT: ud2
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; CHECK-NEXT: LBB1_4: ## %exit
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; CHECK-NEXT: movl $-1, %eax
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; CHECK-NEXT: retq
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entry:
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%start = add i64 %len, -1
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br label %loop
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loop: ; preds = %backedge, %entry
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%iv = phi i64 [ %iv.next, %backedge ], [ %start, %entry ]
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%iv.next = add nsw i64 %iv, -1
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%iv.offset = add i64 %iv, 1
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%iv.next.offset = add i64 %iv.next, 1
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%cond_1 = icmp eq i64 %iv.offset, 0
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br i1 %cond_1, label %exit, label %backedge
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backedge: ; preds = %loop
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%addr = getelementptr inbounds i32, i32* %p, i64 %iv.next.offset
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%loaded = load atomic i32, i32* %addr unordered, align 4
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%cond_2 = icmp eq i32 %loaded, %x
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br i1 %cond_2, label %failure, label %loop
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exit: ; preds = %loop
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ret i32 -1
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failure: ; preds = %backedge
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unreachable
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}
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define i32 @test_03(i32* %p, i64 %len, i32 %x) {
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; CHECK-LABEL: test_03:
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; CHECK: ## %bb.0: ## %entry
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; CHECK-NEXT: .p2align 4, 0x90
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; CHECK-NEXT: LBB2_1: ## %loop
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; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: testq %rsi, %rsi
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; CHECK-NEXT: je LBB2_4
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; CHECK-NEXT: ## %bb.2: ## %backedge
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; CHECK-NEXT: ## in Loop: Header=BB2_1 Depth=1
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; CHECK-NEXT: cmpl %edx, -4(%rdi,%rsi,4)
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; CHECK-NEXT: leaq -1(%rsi), %rsi
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; CHECK-NEXT: jne LBB2_1
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; CHECK-NEXT: ## %bb.3: ## %failure
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; CHECK-NEXT: ud2
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; CHECK-NEXT: LBB2_4: ## %exit
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; CHECK-NEXT: movl $-1, %eax
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; CHECK-NEXT: retq
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entry:
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%start = add i64 %len, -100
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br label %loop
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loop: ; preds = %backedge, %entry
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%iv = phi i64 [ %iv.next, %backedge ], [ %start, %entry ]
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%iv.next = add nsw i64 %iv, -1
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%iv.offset = add i64 %iv, 100
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%iv.next.offset = add i64 %iv.next, 100
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%cond_1 = icmp eq i64 %iv.offset, 0
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br i1 %cond_1, label %exit, label %backedge
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backedge: ; preds = %loop
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%addr = getelementptr inbounds i32, i32* %p, i64 %iv.next.offset
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%loaded = load atomic i32, i32* %addr unordered, align 4
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%cond_2 = icmp eq i32 %loaded, %x
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br i1 %cond_2, label %failure, label %loop
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exit: ; preds = %loop
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ret i32 -1
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failure: ; preds = %backedge
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unreachable
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}
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138
test/Transforms/LoopStrengthReduce/post-increment-insertion.ll
Normal file
138
test/Transforms/LoopStrengthReduce/post-increment-insertion.ll
Normal file
@ -0,0 +1,138 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -loop-reduce -S | FileCheck %s
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target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128-ni:1-p2:32:8:8:32-ni:2"
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target triple = "x86_64-unknown-linux-gnu"
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; FIXME: iv.next is supposed to be inserted in the backedge.
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define i32 @test_01(i32* %p, i64 %len, i32 %x) {
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; CHECK-LABEL: @test_01(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i32, i32* [[P:%.*]], i64 -1
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ], [ [[LEN:%.*]], [[ENTRY:%.*]] ]
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; CHECK-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], -1
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; CHECK-NEXT: [[COND_1:%.*]] = icmp eq i64 [[IV]], 0
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; CHECK-NEXT: br i1 [[COND_1]], label [[EXIT:%.*]], label [[BACKEDGE]]
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; CHECK: backedge:
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; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i32, i32* [[SCEVGEP]], i64 [[IV]]
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; CHECK-NEXT: [[LOADED:%.*]] = load atomic i32, i32* [[SCEVGEP1]] unordered, align 4
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; CHECK-NEXT: [[COND_2:%.*]] = icmp eq i32 [[LOADED]], [[X:%.*]]
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; CHECK-NEXT: br i1 [[COND_2]], label [[FAILURE:%.*]], label [[LOOP]]
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; CHECK: exit:
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; CHECK-NEXT: ret i32 -1
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; CHECK: failure:
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; CHECK-NEXT: unreachable
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;
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entry:
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br label %loop
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loop: ; preds = %backedge, %entry
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%iv = phi i64 [ %iv.next, %backedge ], [ %len, %entry ]
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%iv.next = add nsw i64 %iv, -1
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%cond_1 = icmp eq i64 %iv, 0
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br i1 %cond_1, label %exit, label %backedge
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backedge: ; preds = %loop
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%addr = getelementptr inbounds i32, i32* %p, i64 %iv.next
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%loaded = load atomic i32, i32* %addr unordered, align 4
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%cond_2 = icmp eq i32 %loaded, %x
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br i1 %cond_2, label %failure, label %loop
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exit: ; preds = %loop
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ret i32 -1
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failure: ; preds = %backedge
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unreachable
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}
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define i32 @test_02(i32* %p, i64 %len, i32 %x) {
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; CHECK-LABEL: @test_02(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i32, i32* [[P:%.*]], i64 -1
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[LSR_IV:%.*]] = phi i64 [ [[LSR_IV_NEXT:%.*]], [[BACKEDGE:%.*]] ], [ [[LEN:%.*]], [[ENTRY:%.*]] ]
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; CHECK-NEXT: [[COND_1:%.*]] = icmp eq i64 [[LSR_IV]], 0
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; CHECK-NEXT: br i1 [[COND_1]], label [[EXIT:%.*]], label [[BACKEDGE]]
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; CHECK: backedge:
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; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i32, i32* [[SCEVGEP]], i64 [[LSR_IV]]
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; CHECK-NEXT: [[LOADED:%.*]] = load atomic i32, i32* [[SCEVGEP1]] unordered, align 4
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; CHECK-NEXT: [[COND_2:%.*]] = icmp eq i32 [[LOADED]], [[X:%.*]]
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; CHECK-NEXT: [[LSR_IV_NEXT]] = add i64 [[LSR_IV]], -1
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; CHECK-NEXT: br i1 [[COND_2]], label [[FAILURE:%.*]], label [[LOOP]]
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; CHECK: exit:
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; CHECK-NEXT: ret i32 -1
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; CHECK: failure:
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; CHECK-NEXT: unreachable
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;
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entry:
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%start = add i64 %len, -1
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br label %loop
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loop: ; preds = %backedge, %entry
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%iv = phi i64 [ %iv.next, %backedge ], [ %start, %entry ]
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%iv.next = add nsw i64 %iv, -1
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%iv.offset = add i64 %iv, 1
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%iv.next.offset = add i64 %iv.next, 1
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%cond_1 = icmp eq i64 %iv.offset, 0
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br i1 %cond_1, label %exit, label %backedge
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backedge: ; preds = %loop
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%addr = getelementptr inbounds i32, i32* %p, i64 %iv.next.offset
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%loaded = load atomic i32, i32* %addr unordered, align 4
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%cond_2 = icmp eq i32 %loaded, %x
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br i1 %cond_2, label %failure, label %loop
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exit: ; preds = %loop
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ret i32 -1
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failure: ; preds = %backedge
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unreachable
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}
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define i32 @test_03(i32* %p, i64 %len, i32 %x) {
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; CHECK-LABEL: @test_03(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i32, i32* [[P:%.*]], i64 -1
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[LSR_IV:%.*]] = phi i64 [ [[LSR_IV_NEXT:%.*]], [[BACKEDGE:%.*]] ], [ [[LEN:%.*]], [[ENTRY:%.*]] ]
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; CHECK-NEXT: [[COND_1:%.*]] = icmp eq i64 [[LSR_IV]], 0
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; CHECK-NEXT: br i1 [[COND_1]], label [[EXIT:%.*]], label [[BACKEDGE]]
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; CHECK: backedge:
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; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i32, i32* [[SCEVGEP]], i64 [[LSR_IV]]
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; CHECK-NEXT: [[LOADED:%.*]] = load atomic i32, i32* [[SCEVGEP1]] unordered, align 4
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; CHECK-NEXT: [[COND_2:%.*]] = icmp eq i32 [[LOADED]], [[X:%.*]]
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; CHECK-NEXT: [[LSR_IV_NEXT]] = add i64 [[LSR_IV]], -1
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; CHECK-NEXT: br i1 [[COND_2]], label [[FAILURE:%.*]], label [[LOOP]]
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; CHECK: exit:
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; CHECK-NEXT: ret i32 -1
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; CHECK: failure:
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; CHECK-NEXT: unreachable
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;
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entry:
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%start = add i64 %len, -100
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br label %loop
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loop: ; preds = %backedge, %entry
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%iv = phi i64 [ %iv.next, %backedge ], [ %start, %entry ]
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%iv.next = add nsw i64 %iv, -1
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%iv.offset = add i64 %iv, 100
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%iv.next.offset = add i64 %iv.next, 100
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%cond_1 = icmp eq i64 %iv.offset, 0
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br i1 %cond_1, label %exit, label %backedge
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backedge: ; preds = %loop
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%addr = getelementptr inbounds i32, i32* %p, i64 %iv.next.offset
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%loaded = load atomic i32, i32* %addr unordered, align 4
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%cond_2 = icmp eq i32 %loaded, %x
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br i1 %cond_2, label %failure, label %loop
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exit: ; preds = %loop
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ret i32 -1
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failure: ; preds = %backedge
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unreachable
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}
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