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[Power] Use lwsync for non-seq_cst fences
Summary: hwsync is only required for seq_cst fences, acquire and release one can use the cheaper lwsync. Test Plan: Added some cases to atomics.ll + make check-all Reviewers: jfb, wschmidt Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5317 llvm-svn: 218995
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@ -2549,7 +2549,14 @@ def : Pat<(f64 (extloadf32 xaddr:$src)),
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def : Pat<(f64 (fextend f32:$src)),
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(COPY_TO_REGCLASS $src, F8RC)>;
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def : Pat<(atomic_fence (imm), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
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// Only seq_cst fences require the heavyweight sync (SYNC 0).
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// All others can use the lightweight sync (SYNC 1).
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// source: http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
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// The rule for seq_cst is duplicated to work with both 64 bits and 32 bits
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// versions of Power.
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def : Pat<(atomic_fence (i64 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
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def : Pat<(atomic_fence (i32 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
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def : Pat<(atomic_fence (imm), (imm)), (SYNC 1)>, Requires<[HasSYNC]>;
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def : Pat<(atomic_fence (imm), (imm)), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
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// Additional FNMSUB patterns: -a*c + b == -(a*c - b)
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29
test/CodeGen/PowerPC/atomics-fences.ll
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29
test/CodeGen/PowerPC/atomics-fences.ll
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@ -0,0 +1,29 @@
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; RUN: llc < %s -mtriple=powerpc-apple-darwin -march=ppc32 -verify-machineinstrs | FileCheck %s --check-prefix=CHECK
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; RUN: llc < %s -mtriple=powerpc-apple-darwin -march=ppc64 -verify-machineinstrs | FileCheck %s --check-prefix=CHECK
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; RUN: llc < %s -mtriple=powerpc-apple-darwin -mcpu=440 | FileCheck %s --check-prefix=PPC440
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; Fences
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define void @fence_acquire() {
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; CHECK-LABEL: fence_acquire
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; CHECK: sync 1
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; PPC440-NOT: sync 1
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; PPC440: msync
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fence acquire
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ret void
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}
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define void @fence_release() {
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; CHECK-LABEL: fence_release
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; CHECK: sync 1
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; PPC440-NOT: sync 1
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; PPC440: msync
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fence release
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ret void
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}
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define void @fence_seq_cst() {
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; CHECK-LABEL: fence_seq_cst
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; CHECK: sync 0
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; PPC440-NOT: sync 0
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; PPC440: msync
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fence seq_cst
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ret void
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}
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