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Add codegen support for NEON vst2 intrinsics with <1 x i64> vectors.
llvm-svn: 83513
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@ -1574,6 +1574,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
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case MVT::v4i16: Opc = ARM::VST2d16; break;
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case MVT::v2f32:
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case MVT::v2i32: Opc = ARM::VST2d32; break;
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case MVT::v1i64: Opc = ARM::VST2d64; break;
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}
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SDValue Chain = N->getOperand(0);
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const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
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@ -352,6 +352,9 @@ class VST2Q<bits<4> op7_4, string OpcodeStr>
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def VST2d8 : VST2D<0b0000, "vst2.8">;
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def VST2d16 : VST2D<0b0100, "vst2.16">;
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def VST2d32 : VST2D<0b1000, "vst2.32">;
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def VST2d64 : NLdSt<0,0b00,0b1010,0b1100, (outs),
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(ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST,
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"vst1.64\t\\{$src1,$src2\\}, $addr", "", []>;
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def VST2q8 : VST2Q<0b0000, "vst2.8">;
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def VST2q16 : VST2Q<0b0100, "vst2.16">;
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@ -125,6 +125,7 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs,
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case ARM::VST2d8:
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case ARM::VST2d16:
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case ARM::VST2d32:
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case ARM::VST2d64:
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case ARM::VST2LNd8:
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case ARM::VST2LNd16:
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case ARM::VST2LNd32:
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@ -32,6 +32,14 @@ define void @vst2f(float* %A, <2 x float>* %B) nounwind {
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ret void
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}
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define void @vst2i64(i64* %A, <1 x i64>* %B) nounwind {
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;CHECK: vst2i64:
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;CHECK: vst1.64
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%tmp1 = load <1 x i64>* %B
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call void @llvm.arm.neon.vst2.v1i64(i64* %A, <1 x i64> %tmp1, <1 x i64> %tmp1)
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ret void
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}
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define void @vst2Qi8(i8* %A, <16 x i8>* %B) nounwind {
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;CHECK: vst2Qi8:
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;CHECK: vst2.8
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@ -68,6 +76,7 @@ declare void @llvm.arm.neon.vst2.v8i8(i8*, <8 x i8>, <8 x i8>) nounwind
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declare void @llvm.arm.neon.vst2.v4i16(i8*, <4 x i16>, <4 x i16>) nounwind
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declare void @llvm.arm.neon.vst2.v2i32(i8*, <2 x i32>, <2 x i32>) nounwind
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declare void @llvm.arm.neon.vst2.v2f32(i8*, <2 x float>, <2 x float>) nounwind
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declare void @llvm.arm.neon.vst2.v1i64(i8*, <1 x i64>, <1 x i64>) nounwind
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declare void @llvm.arm.neon.vst2.v16i8(i8*, <16 x i8>, <16 x i8>) nounwind
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declare void @llvm.arm.neon.vst2.v8i16(i8*, <8 x i16>, <8 x i16>) nounwind
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