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[AArch64] Add support for unscaled narrow stores in getUsefulBitsForUse.
llvm-svn: 269263
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@ -1851,12 +1851,14 @@ static void getUsefulBitsForUse(SDNode *UserNode, APInt &UsefulBits,
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return getUsefulBitsFromBFM(SDValue(UserNode, 0), Orig, UsefulBits, Depth);
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return getUsefulBitsFromBFM(SDValue(UserNode, 0), Orig, UsefulBits, Depth);
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case AArch64::STRBBui:
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case AArch64::STRBBui:
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case AArch64::STURBBi:
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if (UserNode->getOperand(0) != Orig)
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if (UserNode->getOperand(0) != Orig)
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return;
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return;
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UsefulBits &= APInt(UsefulBits.getBitWidth(), 0xff);
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UsefulBits &= APInt(UsefulBits.getBitWidth(), 0xff);
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return;
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return;
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case AArch64::STRHHui:
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case AArch64::STRHHui:
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case AArch64::STURHHi:
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if (UserNode->getOperand(0) != Orig)
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if (UserNode->getOperand(0) != Orig)
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return;
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return;
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UsefulBits &= APInt(UsefulBits.getBitWidth(), 0xffff);
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UsefulBits &= APInt(UsefulBits.getBitWidth(), 0xffff);
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@ -273,3 +273,41 @@ entry:
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store i16 %trunc, i16* %ptr16
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store i16 %trunc, i16* %ptr16
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ret void
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ret void
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}
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}
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define void @test_nouseful_sturb(i32* %ptr32, i8* %ptr8, i32 %x) {
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entry:
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; CHECK-LABEL: @test_nouseful_sturb
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; CHECK: ldr [[REG1:w[0-9]+]],
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; CHECK-NOT: and {{w[0-9]+}}, {{w[0-9]+}}, #0xf8
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; CHECK-NEXT: bfxil [[REG1]], w2, #16, #3
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; CHECK-NEXT: sturb [[REG1]],
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; CHECK-NEXT: ret
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%0 = load i32, i32* %ptr32, align 8
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%and = and i32 %0, -8
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%shr = lshr i32 %x, 16
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%and1 = and i32 %shr, 7
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%or = or i32 %and, %and1
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%trunc = trunc i32 %or to i8
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%gep = getelementptr i8, i8* %ptr8, i64 -1
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store i8 %trunc, i8* %gep
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ret void
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}
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define void @test_nouseful_sturh(i32* %ptr32, i16* %ptr16, i32 %x) {
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entry:
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; CHECK-LABEL: @test_nouseful_sturh
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; CHECK: ldr [[REG1:w[0-9]+]],
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; CHECK-NOT: and {{w[0-9]+}}, {{w[0-9]+}}, #0xfff0
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; CHECK-NEXT: bfxil [[REG1]], w2, #16, #4
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; CHECK-NEXT: sturh [[REG1]],
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; CHECK-NEXT: ret
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%0 = load i32, i32* %ptr32, align 8
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%and = and i32 %0, -16
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%shr = lshr i32 %x, 16
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%and1 = and i32 %shr, 15
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%or = or i32 %and, %and1
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%trunc = trunc i32 %or to i16
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%gep = getelementptr i16, i16* %ptr16, i64 -1
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store i16 %trunc, i16* %gep
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ret void
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}
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