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https://github.com/RPCS3/llvm-mirror.git
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[X86] Move frontend CPU feature initialization to a look up table based implementation. NFCI
This replaces the switch statement implementation in the clang's X86.cpp with a lookup table in X86TargetParser.cpp. I've used constexpr and copy of the FeatureBitset from SubtargetFeature.h to store the features in a lookup table. After the lookup the bitset is translated into strings for use by the rest of the frontend code. I had to modify the implementation of the FeatureBitset to avoid bugs in gcc 5.5 constexpr handling. It seems to not like the same array entry to be used on the left side and right hand side of an assignment or &= or |=. I've also used uint32_t instead of uint64_t and sized based on the X86::CPU_FEATURE_MAX. I've initialized the features for different CPUs outside of the table so that we can express inheritance in an adhoc way. This was one of the big limitations of the switch and we had resorted to labels and gotos. Differential Revision: https://reviews.llvm.org/D82731
This commit is contained in:
Craig Topper
parent
b85514f884
commit
9600883c24
@ -125,56 +125,97 @@ X86_CPU_SUBTYPE ("geode", AMDPENTIUM_GEODE)
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// This macro is used for cpu types present in compiler-rt/libgcc.
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#ifndef X86_FEATURE_COMPAT
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#define X86_FEATURE_COMPAT(ENUM, STR) X86_FEATURE(ENUM)
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#define X86_FEATURE_COMPAT(ENUM, STR) X86_FEATURE(ENUM, STR)
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#endif
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#ifndef X86_FEATURE
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#define X86_FEATURE(ENUM)
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#define X86_FEATURE(ENUM, STR)
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#endif
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X86_FEATURE_COMPAT(FEATURE_CMOV, "cmov")
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X86_FEATURE_COMPAT(FEATURE_MMX, "mmx")
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X86_FEATURE_COMPAT(FEATURE_POPCNT, "popcnt")
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X86_FEATURE_COMPAT(FEATURE_SSE, "sse")
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X86_FEATURE_COMPAT(FEATURE_SSE2, "sse2")
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X86_FEATURE_COMPAT(FEATURE_SSE3, "sse3")
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X86_FEATURE_COMPAT(FEATURE_SSSE3, "ssse3")
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X86_FEATURE_COMPAT(FEATURE_SSE4_1, "sse4.1")
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X86_FEATURE_COMPAT(FEATURE_SSE4_2, "sse4.2")
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X86_FEATURE_COMPAT(FEATURE_AVX, "avx")
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X86_FEATURE_COMPAT(FEATURE_AVX2, "avx2")
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X86_FEATURE_COMPAT(FEATURE_SSE4_A, "sse4a")
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X86_FEATURE_COMPAT(FEATURE_FMA4, "fma4")
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X86_FEATURE_COMPAT(FEATURE_XOP, "xop")
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X86_FEATURE_COMPAT(FEATURE_FMA, "fma")
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X86_FEATURE_COMPAT(FEATURE_AVX512F, "avx512f")
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X86_FEATURE_COMPAT(FEATURE_BMI, "bmi")
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X86_FEATURE_COMPAT(FEATURE_BMI2, "bmi2")
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X86_FEATURE_COMPAT(FEATURE_AES, "aes")
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X86_FEATURE_COMPAT(FEATURE_PCLMUL, "pclmul")
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X86_FEATURE_COMPAT(FEATURE_AVX512VL, "avx512vl")
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X86_FEATURE_COMPAT(FEATURE_AVX512BW, "avx512bw")
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X86_FEATURE_COMPAT(FEATURE_AVX512DQ, "avx512dq")
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X86_FEATURE_COMPAT(FEATURE_AVX512CD, "avx512cd")
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X86_FEATURE_COMPAT(FEATURE_AVX512ER, "avx512er")
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X86_FEATURE_COMPAT(FEATURE_AVX512PF, "avx512pf")
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X86_FEATURE_COMPAT(FEATURE_AVX512VBMI, "avx512vbmi")
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X86_FEATURE_COMPAT(FEATURE_AVX512IFMA, "avx512ifma")
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X86_FEATURE_COMPAT(FEATURE_AVX5124VNNIW, "avx5124vnniw")
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X86_FEATURE_COMPAT(FEATURE_AVX5124FMAPS, "avx5124fmaps")
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X86_FEATURE_COMPAT(FEATURE_AVX512VPOPCNTDQ, "avx512vpopcntdq")
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X86_FEATURE_COMPAT(FEATURE_AVX512VBMI2, "avx512vbmi2")
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X86_FEATURE_COMPAT(FEATURE_GFNI, "gfni")
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X86_FEATURE_COMPAT(FEATURE_VPCLMULQDQ, "vpclmulqdq")
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X86_FEATURE_COMPAT(FEATURE_AVX512VNNI, "avx512vnni")
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X86_FEATURE_COMPAT(FEATURE_AVX512BITALG, "avx512bitalg")
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X86_FEATURE_COMPAT(FEATURE_AVX512BF16, "avx512bf16")
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X86_FEATURE_COMPAT(FEATURE_AVX512VP2INTERSECT, "avx512vp2intersect")
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X86_FEATURE_COMPAT(CMOV, "cmov")
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X86_FEATURE_COMPAT(MMX, "mmx")
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X86_FEATURE_COMPAT(POPCNT, "popcnt")
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X86_FEATURE_COMPAT(SSE, "sse")
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X86_FEATURE_COMPAT(SSE2, "sse2")
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X86_FEATURE_COMPAT(SSE3, "sse3")
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X86_FEATURE_COMPAT(SSSE3, "ssse3")
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X86_FEATURE_COMPAT(SSE4_1, "sse4.1")
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X86_FEATURE_COMPAT(SSE4_2, "sse4.2")
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X86_FEATURE_COMPAT(AVX, "avx")
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X86_FEATURE_COMPAT(AVX2, "avx2")
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X86_FEATURE_COMPAT(SSE4_A, "sse4a")
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X86_FEATURE_COMPAT(FMA4, "fma4")
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X86_FEATURE_COMPAT(XOP, "xop")
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X86_FEATURE_COMPAT(FMA, "fma")
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X86_FEATURE_COMPAT(AVX512F, "avx512f")
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X86_FEATURE_COMPAT(BMI, "bmi")
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X86_FEATURE_COMPAT(BMI2, "bmi2")
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X86_FEATURE_COMPAT(AES, "aes")
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X86_FEATURE_COMPAT(PCLMUL, "pclmul")
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X86_FEATURE_COMPAT(AVX512VL, "avx512vl")
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X86_FEATURE_COMPAT(AVX512BW, "avx512bw")
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X86_FEATURE_COMPAT(AVX512DQ, "avx512dq")
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X86_FEATURE_COMPAT(AVX512CD, "avx512cd")
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X86_FEATURE_COMPAT(AVX512ER, "avx512er")
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X86_FEATURE_COMPAT(AVX512PF, "avx512pf")
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X86_FEATURE_COMPAT(AVX512VBMI, "avx512vbmi")
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X86_FEATURE_COMPAT(AVX512IFMA, "avx512ifma")
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X86_FEATURE_COMPAT(AVX5124VNNIW, "avx5124vnniw")
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X86_FEATURE_COMPAT(AVX5124FMAPS, "avx5124fmaps")
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X86_FEATURE_COMPAT(AVX512VPOPCNTDQ, "avx512vpopcntdq")
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X86_FEATURE_COMPAT(AVX512VBMI2, "avx512vbmi2")
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X86_FEATURE_COMPAT(GFNI, "gfni")
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X86_FEATURE_COMPAT(VPCLMULQDQ, "vpclmulqdq")
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X86_FEATURE_COMPAT(AVX512VNNI, "avx512vnni")
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X86_FEATURE_COMPAT(AVX512BITALG, "avx512bitalg")
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X86_FEATURE_COMPAT(AVX512BF16, "avx512bf16")
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X86_FEATURE_COMPAT(AVX512VP2INTERSECT, "avx512vp2intersect")
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// Features below here are not in libgcc/compiler-rt.
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X86_FEATURE (FEATURE_MOVBE)
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X86_FEATURE (FEATURE_ADX)
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X86_FEATURE (FEATURE_EM64T)
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X86_FEATURE (FEATURE_CLFLUSHOPT)
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X86_FEATURE (FEATURE_SHA)
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X86_FEATURE (3DNOW, "3dnow")
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X86_FEATURE (3DNOWA, "3dnowa")
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X86_FEATURE (ADX, "adx")
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X86_FEATURE (CLDEMOTE, "cldemote")
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X86_FEATURE (CLFLUSHOPT, "clflushopt")
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X86_FEATURE (CLWB, "clwb")
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X86_FEATURE (CLZERO, "clzero")
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X86_FEATURE (CMPXCHG16B, "cx16")
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X86_FEATURE (CMPXCHG8B, "cx8")
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X86_FEATURE (EM64T, nullptr)
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X86_FEATURE (ENQCMD, "enqcmd")
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X86_FEATURE (F16C, "f16c")
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X86_FEATURE (FSGSBASE, "fsgsbase")
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X86_FEATURE (FXSR, "fxsr")
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X86_FEATURE (INVPCID, "invpcid")
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X86_FEATURE (LWP, "lwp")
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X86_FEATURE (LZCNT, "lzcnt")
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X86_FEATURE (MOVBE, "movbe")
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X86_FEATURE (MOVDIR64B, "movdir64b")
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X86_FEATURE (MOVDIRI, "movdiri")
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X86_FEATURE (MWAITX, "mwaitx")
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X86_FEATURE (PCONFIG, "pconfig")
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X86_FEATURE (PKU, "pku")
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X86_FEATURE (PREFETCHWT1, "prefetchwt1")
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X86_FEATURE (PRFCHW, "prfchw")
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X86_FEATURE (PTWRITE, "ptwrite")
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X86_FEATURE (RDPID, "rdpid")
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X86_FEATURE (RDRND, "rdrnd")
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X86_FEATURE (RDSEED, "rdseed")
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X86_FEATURE (RTM, "rtm")
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X86_FEATURE (SAHF, "sahf")
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X86_FEATURE (SERIALIZE, "serialize")
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X86_FEATURE (SGX, "sgx")
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X86_FEATURE (SHA, "sha")
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X86_FEATURE (SHSTK, "shstk")
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X86_FEATURE (SSE4A, "sse4a")
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X86_FEATURE (TBM, "tbm")
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X86_FEATURE (TSXLDTRK, "tsxldtrk")
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X86_FEATURE (VAES, "vaes")
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X86_FEATURE (WAITPKG, "waitpkg")
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X86_FEATURE (WBNOINVD, "wbnoinvd")
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X86_FEATURE (X87, "x87")
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X86_FEATURE (XSAVE, "xsave")
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X86_FEATURE (XSAVEC, "xsavec")
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X86_FEATURE (XSAVEOPT, "xsaveopt")
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X86_FEATURE (XSAVES, "xsaves")
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#undef X86_FEATURE_COMPAT
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#undef X86_FEATURE
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@ -53,8 +53,7 @@ enum ProcessorSubtypes : unsigned {
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// This should be kept in sync with libcc/compiler-rt as it should be used
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// by clang as a proxy for what's in libgcc/compiler-rt.
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enum ProcessorFeatures {
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#define X86_FEATURE(ENUM) \
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ENUM,
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#define X86_FEATURE(ENUM, STRING) FEATURE_##ENUM,
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#include "llvm/Support/X86TargetParser.def"
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CPU_FEATURE_MAX
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};
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@ -132,8 +131,12 @@ CPUKind parseArchX86(StringRef CPU, bool Only64Bit = false);
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void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values,
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bool ArchIs32Bit);
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/// Get the key feature prioritizing target multiversioning.
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ProcessorFeatures getKeyFeature(CPUKind Kind);
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/// Fill in the features that \p CPU supports into \p Features.
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void getFeaturesForCPU(StringRef CPU, SmallVectorImpl<StringRef> &Features);
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} // namespace X86
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} // namespace llvm
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@ -19,134 +19,339 @@ using namespace llvm::X86;
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namespace {
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/// Container class for CPU features.
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/// This is a constexpr reimplementation of a subset of std::bitset. It would be
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/// nice to use std::bitset directly, but it doesn't support constant
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/// initialization.
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class FeatureBitset {
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static constexpr unsigned NUM_FEATURE_WORDS =
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(X86::CPU_FEATURE_MAX + 31) / 32;
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// This cannot be a std::array, operator[] is not constexpr until C++17.
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uint32_t Bits[NUM_FEATURE_WORDS] = {};
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public:
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constexpr FeatureBitset() = default;
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constexpr FeatureBitset(std::initializer_list<unsigned> Init) {
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for (auto I : Init)
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set(I);
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}
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constexpr FeatureBitset &set(unsigned I) {
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uint32_t NewBits = Bits[I / 32] | (uint32_t(1) << (I % 32));
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Bits[I / 32] = NewBits;
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return *this;
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}
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constexpr bool operator[](unsigned I) const {
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uint32_t Mask = uint32_t(1) << (I % 32);
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return (Bits[I / 32] & Mask) != 0;
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}
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constexpr FeatureBitset operator&(const FeatureBitset &RHS) const {
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FeatureBitset Result;
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for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
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Result.Bits[I] = Bits[I] & RHS.Bits[I];
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return Result;
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}
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constexpr FeatureBitset operator|(const FeatureBitset &RHS) const {
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FeatureBitset Result;
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for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
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Result.Bits[I] = Bits[I] | RHS.Bits[I];
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return Result;
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}
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constexpr FeatureBitset operator~() const {
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FeatureBitset Result;
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for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
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Result.Bits[I] = ~Bits[I];
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return Result;
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}
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};
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struct ProcInfo {
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StringLiteral Name;
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X86::CPUKind Kind;
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unsigned KeyFeature;
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bool Is64Bit;
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FeatureBitset Features;
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};
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} // end anonymous namespace
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#define PROC_64_BIT true
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#define PROC_32_BIT false
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#define X86_FEATURE(ENUM, STRING) \
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static constexpr FeatureBitset Feature##ENUM = {X86::FEATURE_##ENUM};
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#include "llvm/Support/X86TargetParser.def"
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// Pentium with MMX.
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static constexpr FeatureBitset FeaturesPentiumMMX =
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FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
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// Pentium 2 and 3.
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static constexpr FeatureBitset FeaturesPentium2 =
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FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeatureFXSR;
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static constexpr FeatureBitset FeaturesPentium3 = FeaturesPentium2 | FeatureSSE;
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// Pentium 4 CPUs
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static constexpr FeatureBitset FeaturesPentium4 =
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FeaturesPentium3 | FeatureSSE2;
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static constexpr FeatureBitset FeaturesPrescott =
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FeaturesPentium4 | FeatureSSE3;
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static constexpr FeatureBitset FeaturesNocona =
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FeaturesPrescott | FeatureEM64T | FeatureCMPXCHG16B;
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// Basic 64-bit capable CPU.
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static constexpr FeatureBitset FeaturesX86_64 = FeaturesPentium4 | FeatureEM64T;
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// Intel Core CPUs
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static constexpr FeatureBitset FeaturesCore2 =
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FeaturesNocona | FeatureSAHF | FeatureSSSE3;
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static constexpr FeatureBitset FeaturesPenryn = FeaturesCore2 | FeatureSSE4_1;
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static constexpr FeatureBitset FeaturesNehalem =
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FeaturesPenryn | FeaturePOPCNT | FeatureSSE4_2;
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static constexpr FeatureBitset FeaturesWestmere =
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FeaturesNehalem | FeaturePCLMUL;
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static constexpr FeatureBitset FeaturesSandyBridge =
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FeaturesWestmere | FeatureAVX | FeatureXSAVE | FeatureXSAVEOPT;
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static constexpr FeatureBitset FeaturesIvyBridge =
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FeaturesSandyBridge | FeatureF16C | FeatureFSGSBASE | FeatureRDRND;
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static constexpr FeatureBitset FeaturesHaswell =
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FeaturesIvyBridge | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureFMA |
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FeatureINVPCID | FeatureLZCNT | FeatureMOVBE;
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static constexpr FeatureBitset FeaturesBroadwell =
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FeaturesHaswell | FeatureADX | FeaturePRFCHW | FeatureRDSEED;
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// Intel Knights Landing and Knights Mill
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// Knights Landing has feature parity with Broadwell.
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static constexpr FeatureBitset FeaturesKNL =
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FeaturesBroadwell | FeatureAES | FeatureAVX512F | FeatureAVX512CD |
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FeatureAVX512ER | FeatureAVX512PF | FeaturePREFETCHWT1;
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static constexpr FeatureBitset FeaturesKNM =
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FeaturesKNL | FeatureAVX512VPOPCNTDQ;
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// Intel Skylake processors.
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static constexpr FeatureBitset FeaturesSkylakeClient =
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FeaturesBroadwell | FeatureAES | FeatureCLFLUSHOPT | FeatureXSAVEC |
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FeatureXSAVES | FeatureSGX;
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// SkylakeServer inherits all SkylakeClient features except SGX.
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// FIXME: That doesn't match gcc.
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static constexpr FeatureBitset FeaturesSkylakeServer =
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(FeaturesSkylakeClient & ~FeatureSGX) | FeatureAVX512F | FeatureAVX512CD |
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FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL | FeatureCLWB |
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FeaturePKU;
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static constexpr FeatureBitset FeaturesCascadeLake =
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FeaturesSkylakeServer | FeatureAVX512VNNI;
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static constexpr FeatureBitset FeaturesCooperLake =
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FeaturesCascadeLake | FeatureAVX512BF16;
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// Intel 10nm processors.
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static constexpr FeatureBitset FeaturesCannonlake =
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FeaturesSkylakeClient | FeatureAVX512F | FeatureAVX512CD | FeatureAVX512DQ |
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FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA | FeatureAVX512VBMI |
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FeaturePKU | FeatureSHA;
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static constexpr FeatureBitset FeaturesICLClient =
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FeaturesCannonlake | FeatureAVX512BITALG | FeatureAVX512VBMI2 |
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FeatureAVX512VNNI | FeatureAVX512VPOPCNTDQ | FeatureCLWB | FeatureGFNI |
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FeatureRDPID | FeatureVAES | FeatureVPCLMULQDQ;
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static constexpr FeatureBitset FeaturesICLServer =
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FeaturesICLClient | FeaturePCONFIG | FeatureWBNOINVD;
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static constexpr FeatureBitset FeaturesTigerlake =
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FeaturesICLClient | FeatureAVX512VP2INTERSECT | FeatureMOVDIR64B |
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FeatureMOVDIRI | FeatureSHSTK;
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// Intel Atom processors.
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// Bonnell has feature parity with Core2 and adds MOVBE.
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static constexpr FeatureBitset FeaturesBonnell = FeaturesCore2 | FeatureMOVBE;
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// Silvermont has parity with Westmere and Bonnell plus PRFCHW and RDRND.
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static constexpr FeatureBitset FeaturesSilvermont =
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FeaturesBonnell | FeaturesWestmere | FeaturePRFCHW | FeatureRDRND;
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static constexpr FeatureBitset FeaturesGoldmont =
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FeaturesSilvermont | FeatureAES | FeatureCLFLUSHOPT | FeatureFSGSBASE |
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FeatureRDSEED | FeatureSHA | FeatureXSAVE | FeatureXSAVEC |
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FeatureXSAVEOPT | FeatureXSAVES;
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static constexpr FeatureBitset FeaturesGoldmontPlus =
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FeaturesGoldmont | FeaturePTWRITE | FeatureRDPID | FeatureSGX;
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static constexpr FeatureBitset FeaturesTremont =
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FeaturesGoldmontPlus | FeatureCLWB | FeatureGFNI;
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// Geode Processor.
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static constexpr FeatureBitset FeaturesGeode =
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FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA;
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// K6 processor.
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static constexpr FeatureBitset FeaturesK6 =
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FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
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// K7 and K8 architecture processors.
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static constexpr FeatureBitset FeaturesAthlon =
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FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA;
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static constexpr FeatureBitset FeaturesAthlonXP =
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FeaturesAthlon | FeatureFXSR | FeatureSSE;
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static constexpr FeatureBitset FeaturesK8 =
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FeaturesAthlonXP | FeatureSSE2 | FeatureEM64T;
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static constexpr FeatureBitset FeaturesK8SSE3 = FeaturesK8 | FeatureSSE3;
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static constexpr FeatureBitset FeaturesAMDFAM10 =
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FeaturesK8SSE3 | FeatureCMPXCHG16B | FeatureLZCNT | FeaturePOPCNT |
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FeaturePRFCHW | FeatureSAHF | FeatureSSE4A;
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// Bobcat architecture processors.
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static constexpr FeatureBitset FeaturesBTVER1 =
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FeatureX87 | FeatureCMPXCHG8B | FeatureCMPXCHG16B | FeatureEM64T |
|
||||
FeatureFXSR | FeatureLZCNT | FeatureMMX | FeaturePOPCNT | FeaturePRFCHW |
|
||||
FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4A |
|
||||
FeatureSAHF;
|
||||
static constexpr FeatureBitset FeaturesBTVER2 =
|
||||
FeaturesBTVER1 | FeatureAES | FeatureAVX | FeatureBMI | FeatureF16C |
|
||||
FeatureMOVBE | FeaturePCLMUL | FeatureXSAVE | FeatureXSAVEOPT;
|
||||
|
||||
// AMD Bulldozer architecture processors.
|
||||
static constexpr FeatureBitset FeaturesBDVER1 =
|
||||
FeatureX87 | FeatureAES | FeatureAVX | FeatureCMPXCHG8B |
|
||||
FeatureCMPXCHG16B | FeatureEM64T | FeatureFMA4 | FeatureFXSR |
|
||||
FeatureLZCNT | FeatureLWP | FeatureLZCNT | FeatureMMX | FeaturePCLMUL |
|
||||
FeaturePOPCNT | FeaturePRFCHW | FeatureSAHF | FeatureSSE | FeatureSSE2 |
|
||||
FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 | FeatureSSE4_2 | FeatureSSE4A |
|
||||
FeatureXOP | FeatureXSAVE;
|
||||
static constexpr FeatureBitset FeaturesBDVER2 =
|
||||
FeaturesBDVER1 | FeatureBMI | FeatureFMA | FeatureF16C | FeatureTBM;
|
||||
static constexpr FeatureBitset FeaturesBDVER3 =
|
||||
FeaturesBDVER2 | FeatureFSGSBASE | FeatureXSAVEOPT;
|
||||
static constexpr FeatureBitset FeaturesBDVER4 =
|
||||
FeaturesBDVER3 | FeatureAVX2 | FeatureBMI2 | FeatureMOVBE | FeatureMWAITX |
|
||||
FeatureRDRND;
|
||||
|
||||
// AMD Zen architecture processors.
|
||||
static constexpr FeatureBitset FeaturesZNVER1 =
|
||||
FeatureX87 | FeatureADX | FeatureAES | FeatureAVX | FeatureAVX2 |
|
||||
FeatureBMI | FeatureBMI2 | FeatureCLFLUSHOPT | FeatureCLZERO |
|
||||
FeatureCMPXCHG8B | FeatureCMPXCHG16B | FeatureEM64T | FeatureF16C |
|
||||
FeatureFMA | FeatureFSGSBASE | FeatureFXSR | FeatureLZCNT | FeatureLWP |
|
||||
FeatureLZCNT | FeatureMOVBE | FeatureMMX | FeatureMWAITX | FeaturePCLMUL |
|
||||
FeaturePOPCNT | FeaturePRFCHW | FeatureRDRND | FeatureRDSEED | FeatureSAHF |
|
||||
FeatureSHA | FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 |
|
||||
FeatureSSE4_1 | FeatureSSE4_2 | FeatureSSE4A | FeatureXSAVE |
|
||||
FeatureXSAVEC | FeatureXSAVEOPT | FeatureXSAVES;
|
||||
static constexpr FeatureBitset FeaturesZNVER2 =
|
||||
FeaturesZNVER1 | FeatureCLWB | FeatureRDPID | FeatureWBNOINVD;
|
||||
|
||||
static constexpr ProcInfo Processors[] = {
|
||||
// Empty processor. Include X87 and CMPXCHG8 for backwards compatibility.
|
||||
{ {""}, CK_None, ~0U, FeatureX87 | FeatureCMPXCHG8B },
|
||||
// i386-generation processors.
|
||||
{ {"i386"}, CK_i386, ~0U, PROC_32_BIT },
|
||||
{ {"i386"}, CK_i386, ~0U, FeatureX87 },
|
||||
// i486-generation processors.
|
||||
{ {"i486"}, CK_i486, ~0U, PROC_32_BIT },
|
||||
{ {"winchip-c6"}, CK_WinChipC6, ~0U, PROC_32_BIT },
|
||||
{ {"winchip2"}, CK_WinChip2, ~0U, PROC_32_BIT },
|
||||
{ {"c3"}, CK_C3, ~0U, PROC_32_BIT },
|
||||
{ {"i486"}, CK_i486, ~0U, FeatureX87 },
|
||||
{ {"winchip-c6"}, CK_WinChipC6, ~0U, FeaturesPentiumMMX },
|
||||
{ {"winchip2"}, CK_WinChip2, ~0U, FeaturesPentiumMMX | Feature3DNOW },
|
||||
{ {"c3"}, CK_C3, ~0U, FeaturesPentiumMMX | Feature3DNOW },
|
||||
// i586-generation processors, P5 microarchitecture based.
|
||||
{ {"i586"}, CK_i586, ~0U, PROC_32_BIT },
|
||||
{ {"pentium"}, CK_Pentium, ~0U, PROC_32_BIT },
|
||||
{ {"pentium-mmx"}, CK_PentiumMMX, ~0U, PROC_32_BIT },
|
||||
{ {"pentiumpro"}, CK_PentiumPro, ~0U, PROC_32_BIT },
|
||||
{ {"i586"}, CK_i586, ~0U, FeatureX87 | FeatureCMPXCHG8B },
|
||||
{ {"pentium"}, CK_Pentium, ~0U, FeatureX87 | FeatureCMPXCHG8B },
|
||||
{ {"pentium-mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX },
|
||||
// i686-generation processors, P6 / Pentium M microarchitecture based.
|
||||
{ {"i686"}, CK_i686, ~0U, PROC_32_BIT },
|
||||
{ {"pentium2"}, CK_Pentium2, ~0U, PROC_32_BIT },
|
||||
{ {"pentium3"}, CK_Pentium3, ~0U, PROC_32_BIT },
|
||||
{ {"pentium3m"}, CK_Pentium3, ~0U, PROC_32_BIT },
|
||||
{ {"pentium-m"}, CK_PentiumM, ~0U, PROC_32_BIT },
|
||||
{ {"c3-2"}, CK_C3_2, ~0U, PROC_32_BIT },
|
||||
{ {"yonah"}, CK_Yonah, ~0U, PROC_32_BIT },
|
||||
{ {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureX87 | FeatureCMPXCHG8B },
|
||||
{ {"i686"}, CK_i686, ~0U, FeatureX87 | FeatureCMPXCHG8B },
|
||||
{ {"pentium2"}, CK_Pentium2, ~0U, FeaturesPentium2 },
|
||||
{ {"pentium3"}, CK_Pentium3, ~0U, FeaturesPentium3 },
|
||||
{ {"pentium3m"}, CK_Pentium3, ~0U, FeaturesPentium3 },
|
||||
{ {"pentium-m"}, CK_PentiumM, ~0U, FeaturesPentium4 },
|
||||
{ {"c3-2"}, CK_C3_2, ~0U, FeaturesPentium3 },
|
||||
{ {"yonah"}, CK_Yonah, ~0U, FeaturesPrescott },
|
||||
// Netburst microarchitecture based processors.
|
||||
{ {"pentium4"}, CK_Pentium4, ~0U, PROC_32_BIT },
|
||||
{ {"pentium4m"}, CK_Pentium4, ~0U, PROC_32_BIT },
|
||||
{ {"prescott"}, CK_Prescott, ~0U, PROC_32_BIT },
|
||||
{ {"nocona"}, CK_Nocona, ~0U, PROC_64_BIT },
|
||||
{ {"pentium4"}, CK_Pentium4, ~0U, FeaturesPentium4 },
|
||||
{ {"pentium4m"}, CK_Pentium4, ~0U, FeaturesPentium4 },
|
||||
{ {"prescott"}, CK_Prescott, ~0U, FeaturesPrescott },
|
||||
{ {"nocona"}, CK_Nocona, ~0U, FeaturesNocona },
|
||||
// Core microarchitecture based processors.
|
||||
{ {"core2"}, CK_Core2, ~0U, PROC_64_BIT },
|
||||
{ {"penryn"}, CK_Penryn, ~0U, PROC_64_BIT },
|
||||
{ {"core2"}, CK_Core2, ~0U, FeaturesCore2 },
|
||||
{ {"penryn"}, CK_Penryn, ~0U, FeaturesPenryn },
|
||||
// Atom processors
|
||||
{ {"bonnell"}, CK_Bonnell, FEATURE_SSSE3, PROC_64_BIT },
|
||||
{ {"atom"}, CK_Bonnell, FEATURE_SSSE3, PROC_64_BIT },
|
||||
{ {"silvermont"}, CK_Silvermont, FEATURE_SSE4_2, PROC_64_BIT },
|
||||
{ {"slm"}, CK_Silvermont, FEATURE_SSE4_2, PROC_64_BIT },
|
||||
{ {"goldmont"}, CK_Goldmont, FEATURE_SSE4_2, PROC_64_BIT },
|
||||
{ {"goldmont-plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, PROC_64_BIT },
|
||||
{ {"tremont"}, CK_Tremont, FEATURE_SSE4_2, PROC_64_BIT },
|
||||
{ {"bonnell"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell },
|
||||
{ {"atom"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell },
|
||||
{ {"silvermont"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont },
|
||||
{ {"slm"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont },
|
||||
{ {"goldmont"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont },
|
||||
{ {"goldmont-plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus },
|
||||
{ {"tremont"}, CK_Tremont, FEATURE_SSE4_2, FeaturesTremont },
|
||||
// Nehalem microarchitecture based processors.
|
||||
{ {"nehalem"}, CK_Nehalem, FEATURE_SSE4_2, PROC_64_BIT },
|
||||
{ {"corei7"}, CK_Nehalem, FEATURE_SSE4_2, PROC_64_BIT },
|
||||
{ {"nehalem"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem },
|
||||
{ {"corei7"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem },
|
||||
// Westmere microarchitecture based processors.
|
||||
{ {"westmere"}, CK_Westmere, FEATURE_PCLMUL, PROC_64_BIT },
|
||||
{ {"westmere"}, CK_Westmere, FEATURE_PCLMUL, FeaturesWestmere },
|
||||
// Sandy Bridge microarchitecture based processors.
|
||||
{ {"sandybridge"}, CK_SandyBridge, FEATURE_AVX, PROC_64_BIT },
|
||||
{ {"corei7-avx"}, CK_SandyBridge, FEATURE_AVX, PROC_64_BIT },
|
||||
{ {"sandybridge"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge },
|
||||
{ {"corei7-avx"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge },
|
||||
// Ivy Bridge microarchitecture based processors.
|
||||
{ {"ivybridge"}, CK_IvyBridge, FEATURE_AVX, PROC_64_BIT },
|
||||
{ {"core-avx-i"}, CK_IvyBridge, FEATURE_AVX, PROC_64_BIT },
|
||||
{ {"ivybridge"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge },
|
||||
{ {"core-avx-i"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge },
|
||||
// Haswell microarchitecture based processors.
|
||||
{ {"haswell"}, CK_Haswell, FEATURE_AVX2, PROC_64_BIT },
|
||||
{ {"core-avx2"}, CK_Haswell, FEATURE_AVX2, PROC_64_BIT },
|
||||
{ {"haswell"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell },
|
||||
{ {"core-avx2"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell },
|
||||
// Broadwell microarchitecture based processors.
|
||||
{ {"broadwell"}, CK_Broadwell, FEATURE_AVX2, PROC_64_BIT },
|
||||
{ {"broadwell"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell },
|
||||
// Skylake client microarchitecture based processors.
|
||||
{ {"skylake"}, CK_SkylakeClient, FEATURE_AVX2, PROC_64_BIT },
|
||||
{ {"skylake"}, CK_SkylakeClient, FEATURE_AVX2, FeaturesSkylakeClient },
|
||||
// Skylake server microarchitecture based processors.
|
||||
{ {"skylake-avx512"}, CK_SkylakeServer, FEATURE_AVX512F, PROC_64_BIT },
|
||||
{ {"skx"}, CK_SkylakeServer, FEATURE_AVX512F, PROC_64_BIT },
|
||||
{ {"skylake-avx512"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer },
|
||||
{ {"skx"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer },
|
||||
// Cascadelake Server microarchitecture based processors.
|
||||
{ {"cascadelake"}, CK_Cascadelake, FEATURE_AVX512VNNI, PROC_64_BIT },
|
||||
{ {"cascadelake"}, CK_Cascadelake, FEATURE_AVX512VNNI, FeaturesCascadeLake },
|
||||
// Cooperlake Server microarchitecture based processors.
|
||||
{ {"cooperlake"}, CK_Cooperlake, FEATURE_AVX512BF16, PROC_64_BIT },
|
||||
{ {"cooperlake"}, CK_Cooperlake, FEATURE_AVX512BF16, FeaturesCooperLake },
|
||||
// Cannonlake client microarchitecture based processors.
|
||||
{ {"cannonlake"}, CK_Cannonlake, FEATURE_AVX512VBMI, PROC_64_BIT },
|
||||
{ {"cannonlake"}, CK_Cannonlake, FEATURE_AVX512VBMI, FeaturesCannonlake },
|
||||
// Icelake client microarchitecture based processors.
|
||||
{ {"icelake-client"}, CK_IcelakeClient, FEATURE_AVX512VBMI2, PROC_64_BIT },
|
||||
{ {"icelake-client"}, CK_IcelakeClient, FEATURE_AVX512VBMI2, FeaturesICLClient },
|
||||
// Icelake server microarchitecture based processors.
|
||||
{ {"icelake-server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, PROC_64_BIT },
|
||||
{ {"icelake-server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, FeaturesICLServer },
|
||||
// Tigerlake microarchitecture based processors.
|
||||
{ {"tigerlake"}, CK_Tigerlake, FEATURE_AVX512VP2INTERSECT, PROC_64_BIT },
|
||||
{ {"tigerlake"}, CK_Tigerlake, FEATURE_AVX512VP2INTERSECT, FeaturesTigerlake },
|
||||
// Knights Landing processor.
|
||||
{ {"knl"}, CK_KNL, FEATURE_AVX512F, PROC_64_BIT },
|
||||
{ {"knl"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL },
|
||||
// Knights Mill processor.
|
||||
{ {"knm"}, CK_KNM, FEATURE_AVX5124FMAPS, PROC_64_BIT },
|
||||
{ {"knm"}, CK_KNM, FEATURE_AVX5124FMAPS, FeaturesKNM },
|
||||
// Lakemont microarchitecture based processors.
|
||||
{ {"lakemont"}, CK_Lakemont, ~0U, PROC_32_BIT },
|
||||
{ {"lakemont"}, CK_Lakemont, ~0U, FeatureCMPXCHG8B },
|
||||
// K6 architecture processors.
|
||||
{ {"k6"}, CK_K6, ~0U, PROC_32_BIT },
|
||||
{ {"k6-2"}, CK_K6_2, ~0U, PROC_32_BIT },
|
||||
{ {"k6-3"}, CK_K6_3, ~0U, PROC_32_BIT },
|
||||
{ {"k6"}, CK_K6, ~0U, FeaturesK6 },
|
||||
{ {"k6-2"}, CK_K6_2, ~0U, FeaturesK6 | Feature3DNOW },
|
||||
{ {"k6-3"}, CK_K6_3, ~0U, FeaturesK6 | Feature3DNOW },
|
||||
// K7 architecture processors.
|
||||
{ {"athlon"}, CK_Athlon, ~0U, PROC_32_BIT },
|
||||
{ {"athlon-tbird"}, CK_Athlon, ~0U, PROC_32_BIT },
|
||||
{ {"athlon-xp"}, CK_AthlonXP, ~0U, PROC_32_BIT },
|
||||
{ {"athlon-mp"}, CK_AthlonXP, ~0U, PROC_32_BIT },
|
||||
{ {"athlon-4"}, CK_AthlonXP, ~0U, PROC_32_BIT },
|
||||
{ {"athlon"}, CK_Athlon, ~0U, FeaturesAthlon },
|
||||
{ {"athlon-tbird"}, CK_Athlon, ~0U, FeaturesAthlon },
|
||||
{ {"athlon-xp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
|
||||
{ {"athlon-mp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
|
||||
{ {"athlon-4"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
|
||||
// K8 architecture processors.
|
||||
{ {"k8"}, CK_K8, ~0U, PROC_64_BIT },
|
||||
{ {"athlon64"}, CK_K8, ~0U, PROC_64_BIT },
|
||||
{ {"athlon-fx"}, CK_K8, ~0U, PROC_64_BIT },
|
||||
{ {"opteron"}, CK_K8, ~0U, PROC_64_BIT },
|
||||
{ {"k8-sse3"}, CK_K8SSE3, ~0U, PROC_64_BIT },
|
||||
{ {"athlon64-sse3"}, CK_K8SSE3, ~0U, PROC_64_BIT },
|
||||
{ {"opteron-sse3"}, CK_K8SSE3, ~0U, PROC_64_BIT },
|
||||
{ {"amdfam10"}, CK_AMDFAM10, FEATURE_SSE4_A, PROC_64_BIT },
|
||||
{ {"barcelona"}, CK_AMDFAM10, FEATURE_SSE4_A, PROC_64_BIT },
|
||||
{ {"k8"}, CK_K8, ~0U, FeaturesK8 },
|
||||
{ {"athlon64"}, CK_K8, ~0U, FeaturesK8 },
|
||||
{ {"athlon-fx"}, CK_K8, ~0U, FeaturesK8 },
|
||||
{ {"opteron"}, CK_K8, ~0U, FeaturesK8 },
|
||||
{ {"k8-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
|
||||
{ {"athlon64-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
|
||||
{ {"opteron-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
|
||||
{ {"amdfam10"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 },
|
||||
{ {"barcelona"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 },
|
||||
// Bobcat architecture processors.
|
||||
{ {"btver1"}, CK_BTVER1, FEATURE_SSE4_A, PROC_64_BIT },
|
||||
{ {"btver2"}, CK_BTVER2, FEATURE_BMI, PROC_64_BIT },
|
||||
{ {"btver1"}, CK_BTVER1, FEATURE_SSE4_A, FeaturesBTVER1 },
|
||||
{ {"btver2"}, CK_BTVER2, FEATURE_BMI, FeaturesBTVER2 },
|
||||
// Bulldozer architecture processors.
|
||||
{ {"bdver1"}, CK_BDVER1, FEATURE_XOP, PROC_64_BIT },
|
||||
{ {"bdver2"}, CK_BDVER2, FEATURE_FMA, PROC_64_BIT },
|
||||
{ {"bdver3"}, CK_BDVER3, FEATURE_FMA, PROC_64_BIT },
|
||||
{ {"bdver4"}, CK_BDVER4, FEATURE_AVX2, PROC_64_BIT },
|
||||
{ {"bdver1"}, CK_BDVER1, FEATURE_XOP, FeaturesBDVER1 },
|
||||
{ {"bdver2"}, CK_BDVER2, FEATURE_FMA, FeaturesBDVER2 },
|
||||
{ {"bdver3"}, CK_BDVER3, FEATURE_FMA, FeaturesBDVER3 },
|
||||
{ {"bdver4"}, CK_BDVER4, FEATURE_AVX2, FeaturesBDVER4 },
|
||||
// Zen architecture processors.
|
||||
{ {"znver1"}, CK_ZNVER1, FEATURE_AVX2, PROC_64_BIT },
|
||||
{ {"znver2"}, CK_ZNVER2, FEATURE_AVX2, PROC_64_BIT },
|
||||
{ {"znver1"}, CK_ZNVER1, FEATURE_AVX2, FeaturesZNVER1 },
|
||||
{ {"znver2"}, CK_ZNVER2, FEATURE_AVX2, FeaturesZNVER2 },
|
||||
// Generic 64-bit processor.
|
||||
{ {"x86-64"}, CK_x86_64, ~0U, PROC_64_BIT },
|
||||
{ {"x86-64"}, CK_x86_64, ~0U, FeaturesX86_64 },
|
||||
// Geode processors.
|
||||
{ {"geode"}, CK_Geode, ~0U, PROC_32_BIT },
|
||||
{ {"geode"}, CK_Geode, ~0U, FeaturesGeode },
|
||||
};
|
||||
|
||||
X86::CPUKind llvm::X86::parseArchX86(StringRef CPU, bool Only64Bit) {
|
||||
for (const auto &P : Processors)
|
||||
if (P.Name == CPU && (P.Is64Bit || !Only64Bit))
|
||||
if (P.Name == CPU && (P.Features[FEATURE_EM64T] || !Only64Bit))
|
||||
return P.Kind;
|
||||
|
||||
return CK_None;
|
||||
@ -155,7 +360,7 @@ X86::CPUKind llvm::X86::parseArchX86(StringRef CPU, bool Only64Bit) {
|
||||
void llvm::X86::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values,
|
||||
bool Only64Bit) {
|
||||
for (const auto &P : Processors)
|
||||
if (P.Is64Bit || !Only64Bit)
|
||||
if (!P.Name.empty() && (P.Features[FEATURE_EM64T] || !Only64Bit))
|
||||
Values.emplace_back(P.Name);
|
||||
}
|
||||
|
||||
@ -171,3 +376,20 @@ ProcessorFeatures llvm::X86::getKeyFeature(X86::CPUKind Kind) {
|
||||
|
||||
llvm_unreachable("Unable to find CPU kind!");
|
||||
}
|
||||
|
||||
static const char *FeatureStrings[X86::CPU_FEATURE_MAX] = {
|
||||
#define X86_FEATURE(ENUM, STR) STR,
|
||||
#include "llvm/Support/X86TargetParser.def"
|
||||
};
|
||||
|
||||
void llvm::X86::getFeaturesForCPU(StringRef CPU,
|
||||
SmallVectorImpl<StringRef> &Features) {
|
||||
auto I = llvm::find_if(Processors,
|
||||
[&](const ProcInfo &P) { return P.Name == CPU; });
|
||||
assert(I != std::end(Processors) && "Processor not found!");
|
||||
|
||||
// Add the string version of all set bits.
|
||||
for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
|
||||
if (FeatureStrings[i] && I->Features[i])
|
||||
Features.push_back(FeatureStrings[i]);
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user