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Fix encoding of the immediate operands on post-indexed LDR and friends.
llvm-svn: 121354
This commit is contained in:
Owen Anderson
parent
3d9fc7db03
commit
96545f21b9
@ -1310,74 +1310,61 @@ def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
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// Indexed loads
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class T2Iidxld<bit signed, bits<2> opcod, bit pre,
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dag oops, dag iops,
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AddrMode am, IndexMode im, InstrItinClass itin,
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string opc, string asm, string cstr, list<dag> pattern>
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: T2Iidxldst<signed, opcod, 1, pre, oops,
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iops, am,im,itin, opc, asm, cstr, pattern>;
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class T2Iidxst<bit signed, bits<2> opcod, bit pre,
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dag oops, dag iops,
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AddrMode am, IndexMode im, InstrItinClass itin,
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string opc, string asm, string cstr, list<dag> pattern>
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: T2Iidxldst<signed, opcod, 0, pre, oops,
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iops, am,im,itin, opc, asm, cstr, pattern>;
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let mayLoad = 1, neverHasSideEffects = 1 in {
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def t2LDR_PRE : T2Iidxld<0, 0b10, 1, (outs GPR:$Rt, GPR:$Rn),
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def t2LDR_PRE : T2Iidxldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn),
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(ins t2addrmode_imm8:$addr),
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AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
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"ldr", "\t$Rt, $addr!", "$addr.base = $Rn",
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[]>;
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def t2LDR_POST : T2Iidxld<0, 0b10, 0, (outs GPR:$Rt, GPR:$Rn),
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(ins GPR:$base, t2am_imm8_offset:$offset),
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def t2LDR_POST : T2Iidxldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn),
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(ins GPR:$base, t2am_imm8_offset:$addr),
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AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,
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"ldr", "\t$Rt, [$Rn], $offset", "$base = $Rn",
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"ldr", "\t$Rt, [$Rn], $addr", "$base = $Rn",
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[]>;
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def t2LDRB_PRE : T2Iidxld<0, 0b00, 1, (outs GPR:$Rt, GPR:$Rn),
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def t2LDRB_PRE : T2Iidxldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn),
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(ins t2addrmode_imm8:$addr),
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AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
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"ldrb", "\t$Rt, $addr!", "$addr.base = $Rn",
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[]>;
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def t2LDRB_POST : T2Iidxld<0, 0b00, 0, (outs GPR:$Rt, GPR:$Rn),
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(ins GPR:$base, t2am_imm8_offset:$offset),
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def t2LDRB_POST : T2Iidxldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn),
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(ins GPR:$base, t2am_imm8_offset:$addr),
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AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
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"ldrb", "\t$Rt, [$Rn], $offset", "$base = $Rn",
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"ldrb", "\t$Rt, [$Rn], $addr", "$base = $Rn",
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[]>;
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def t2LDRH_PRE : T2Iidxld<0, 0b01, 1, (outs GPR:$Rt, GPR:$Rn),
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def t2LDRH_PRE : T2Iidxldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn),
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(ins t2addrmode_imm8:$addr),
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AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
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"ldrh", "\t$Rt, $addr!", "$addr.base = $Rn",
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[]>;
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def t2LDRH_POST : T2Iidxld<0, 0b01, 0, (outs GPR:$Rt, GPR:$Rn),
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(ins GPR:$base, t2am_imm8_offset:$offset),
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def t2LDRH_POST : T2Iidxldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn),
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(ins GPR:$base, t2am_imm8_offset:$addr),
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AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
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"ldrh", "\t$Rt, [$Rn], $offset", "$base = $Rn",
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"ldrh", "\t$Rt, [$Rn], $addr", "$base = $Rn",
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[]>;
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def t2LDRSB_PRE : T2Iidxld<1, 0b00, 1, (outs GPR:$Rt, GPR:$Rn),
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def t2LDRSB_PRE : T2Iidxldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn),
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(ins t2addrmode_imm8:$addr),
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AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
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"ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn",
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[]>;
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def t2LDRSB_POST : T2Iidxld<1, 0b00, 0, (outs GPR:$Rt, GPR:$Rn),
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(ins GPR:$base, t2am_imm8_offset:$offset),
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def t2LDRSB_POST : T2Iidxldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn),
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(ins GPR:$base, t2am_imm8_offset:$addr),
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AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
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"ldrsb", "\t$Rt, [$Rn], $offset", "$base = $Rn",
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"ldrsb", "\t$Rt, [$Rn], $addr", "$base = $Rn",
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[]>;
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def t2LDRSH_PRE : T2Iidxld<1, 0b01, 1, (outs GPR:$Rt, GPR:$Rn),
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def t2LDRSH_PRE : T2Iidxldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn),
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(ins t2addrmode_imm8:$addr),
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AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
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"ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn",
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[]>;
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def t2LDRSH_POST : T2Iidxld<1, 0b01, 0, (outs GPR:$dst, GPR:$Rn),
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(ins GPR:$base, t2am_imm8_offset:$offset),
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def t2LDRSH_POST : T2Iidxldst<1, 0b01, 1, 0, (outs GPR:$dst, GPR:$Rn),
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(ins GPR:$base, t2am_imm8_offset:$addr),
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AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
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"ldrsh", "\t$dst, [$Rn], $offset", "$base = $Rn",
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"ldrsh", "\t$dst, [$Rn], $addr", "$base = $Rn",
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[]>;
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} // mayLoad = 1, neverHasSideEffects = 1
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@ -1424,42 +1411,42 @@ def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
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IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>;
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// Indexed stores
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def t2STR_PRE : T2Iidxst<0, 0b10, 1, (outs GPR:$base_wb),
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def t2STR_PRE : T2Iidxldst<0, 0b10, 0, 1, (outs GPR:$base_wb),
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(ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
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AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
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"str", "\t$Rt, [$Rn, $addr]!", "$Rn = $base_wb",
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[(set GPR:$base_wb,
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(pre_store GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
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def t2STR_POST : T2Iidxst<0, 0b10, 0, (outs GPR:$base_wb),
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def t2STR_POST : T2Iidxldst<0, 0b10, 0, 0, (outs GPR:$base_wb),
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(ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
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AddrModeT2_i8, IndexModePost, IIC_iStore_iu,
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"str", "\t$Rt, [$Rn], $addr", "$Rn = $base_wb",
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[(set GPR:$base_wb,
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(post_store GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
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def t2STRH_PRE : T2Iidxst<0, 0b01, 1, (outs GPR:$base_wb),
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def t2STRH_PRE : T2Iidxldst<0, 0b01, 0, 1, (outs GPR:$base_wb),
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(ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
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AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
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"strh", "\t$Rt, [$Rn, $addr]!", "$Rn = $base_wb",
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[(set GPR:$base_wb,
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(pre_truncsti16 GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
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def t2STRH_POST : T2Iidxst<0, 0b01, 0, (outs GPR:$base_wb),
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def t2STRH_POST : T2Iidxldst<0, 0b01, 0, 0, (outs GPR:$base_wb),
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(ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
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AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
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"strh", "\t$Rt, [$Rn], $addr", "$Rn = $base_wb",
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[(set GPR:$base_wb,
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(post_truncsti16 GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
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def t2STRB_PRE : T2Iidxst<0, 0b00, 1, (outs GPR:$base_wb),
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def t2STRB_PRE : T2Iidxldst<0, 0b00, 0, 1, (outs GPR:$base_wb),
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(ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
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AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
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"strb", "\t$Rt, [$Rn, $addr]!", "$Rn = $base_wb",
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[(set GPR:$base_wb,
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(pre_truncsti8 GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
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def t2STRB_POST : T2Iidxst<0, 0b00, 0, (outs GPR:$base_wb),
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def t2STRB_POST : T2Iidxldst<0, 0b00, 0, 0, (outs GPR:$base_wb),
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(ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
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AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
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"strb", "\t$Rt, [$Rn], $addr", "$Rn = $base_wb",
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