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[Hexagon] Fixes and updates to the selection patterns
- Add some missing patterns. - Use C4_cmplte in branch patterns. - Fix signedness of immediate operand in M2_accii. llvm-svn: 305085
This commit is contained in:
Krzysztof Parzyszek
parent
e37b726243
commit
967a1babc9
@ -354,7 +354,7 @@ def: Pat<(add (mul IntRegs:$src2, u32_0ImmPred:$src3), IntRegs:$src1),
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(M2_macsip IntRegs:$src1, IntRegs:$src2, imm:$src3)>;
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def: Pat<(add (mul I32:$src2, I32:$src3), I32:$src1),
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(M2_maci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
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def: Pat<(add (add IntRegs:$src2, u32_0ImmPred:$src3), IntRegs:$src1),
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def: Pat<(add (add IntRegs:$src2, s32_0ImmPred:$src3), IntRegs:$src1),
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(M2_accii IntRegs:$src1, IntRegs:$src2, imm:$src3)>;
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def: Pat<(add (add I32:$src2, I32:$src3), I32:$src1),
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(M2_acci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
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@ -683,6 +683,8 @@ def I32toI1: OutPatFrag<(ops node:$Rs),
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defm: Storexm_pat<store, I1, s32_0ImmPred, I1toI32, S2_storerb_io>;
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def: Storexm_simple_pat<store, I1, I1toI32, S2_storerb_io>;
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def: Pat<(sra (add (sra I64:$src, u6_0ImmPred:$u6), 1), (i32 1)),
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(S2_asr_i_p_rnd DoubleRegs:$src, imm:$u6)>, Requires<[HasV5T]>;
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def: Pat<(sra I64:$src, u6_0ImmPred:$u6),
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(S2_asr_i_p DoubleRegs:$src, imm:$u6)>;
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def: Pat<(srl I64:$src, u6_0ImmPred:$u6),
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@ -795,27 +797,19 @@ def: Pat<(i64 (sext_inreg I64:$src1, i16)),
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def: Pat<(i64 (sext_inreg I64:$src1, i8)),
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(A2_sxtw (A2_sxtb (LoReg DoubleRegs:$src1)))>;
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// We want to prevent emitting pnot's as much as possible.
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// Map brcond with an unsupported setcc to a J2_jumpf.
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def : Pat <(brcond (i1 (setne I32:$src1, I32:$src2)),
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bb:$offset),
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(J2_jumpf (C2_cmpeq I32:$src1, I32:$src2),
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bb:$offset)>;
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def : Pat <(brcond (i1 (setne I32:$src1, s10_0ImmPred:$src2)),
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bb:$offset),
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(J2_jumpf (C2_cmpeqi I32:$src1, s10_0ImmPred:$src2), bb:$offset)>;
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def: Pat<(brcond (i1 (setne I1:$src1, (i1 -1))), bb:$offset),
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(J2_jumpf PredRegs:$src1, bb:$offset)>;
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def: Pat<(brcond (i1 (setne I1:$src1, (i1 0))), bb:$offset),
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(J2_jumpt PredRegs:$src1, bb:$offset)>;
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def: Pat<(brcond (i1 (setne I32:$Rs, I32:$Rt)), bb:$offset),
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(J2_jumpf (C2_cmpeq I32:$Rs, I32:$Rt), bb:$offset)>;
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def: Pat<(brcond (i1 (setne I32:$Rs, s10_0ImmPred:$s10)), bb:$offset),
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(J2_jumpf (C2_cmpeqi I32:$Rs, imm:$s10), bb:$offset)>;
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def: Pat<(brcond (i1 (setne I1:$Pu, (i1 -1))), bb:$offset),
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(J2_jumpf PredRegs:$Pu, bb:$offset)>;
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def: Pat<(brcond (i1 (setne I1:$Pu, (i1 0))), bb:$offset),
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(J2_jumpt PredRegs:$Pu, bb:$offset)>;
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// cmp.lt(Rs, Imm) -> !cmp.ge(Rs, Imm) -> !cmp.gt(Rs, Imm-1)
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def: Pat<(brcond (i1 (setlt I32:$src1, s8_0ImmPred:$src2)), bb:$offset),
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(J2_jumpf (C2_cmpgti IntRegs:$src1, (SDEC1 s8_0ImmPred:$src2)),
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bb:$offset)>;
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def: Pat<(brcond (i1 (setlt I32:$Rs, s8_0ImmPred:$s8)), bb:$offset),
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(J2_jumpf (C2_cmpgti IntRegs:$Rs, (SDEC1 imm:$s8)), bb:$offset)>;
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// Map from a 64-bit select to an emulated 64-bit mux.
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// Hexagon does not support 64-bit MUXes; so emulate with combines.
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@ -869,15 +863,13 @@ def: Pat<(i1 (setne I1:$src1, I1:$src2)),
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def: Pat<(i1 (setne I64:$src1, I64:$src2)),
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(C2_not (C2_cmpeqp DoubleRegs:$src1, DoubleRegs:$src2))>;
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// Map cmpge(Rs, Rt) -> !cmpgt(Rs, Rt).
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// rs >= rt -> !(rt > rs).
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def : Pat <(i1 (setge I32:$src1, I32:$src2)),
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(i1 (C2_not (i1 (C2_cmpgt I32:$src2, I32:$src1))))>;
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// rs >= rt -> rt <= rs
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def: Pat<(i1 (setge I32:$Rs, I32:$Rt)),
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(C4_cmplte I32:$Rt, I32:$Rs)>;
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// cmpge(Rs, Imm) -> cmpgt(Rs, Imm-1)
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let AddedComplexity = 30 in
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def: Pat<(i1 (setge I32:$src1, s32_0ImmPred:$src2)),
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(C2_cmpgti IntRegs:$src1, (SDEC1 s32_0ImmPred:$src2))>;
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def: Pat<(i1 (setge I32:$Rs, s32_0ImmPred:$s10)),
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(C2_cmpgti IntRegs:$Rs, (SDEC1 imm:$s10))>;
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// Map cmpge(Rss, Rtt) -> !cmpgt(Rtt, Rss).
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// rss >= rtt -> !(rtt > rss).
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@ -1643,9 +1635,14 @@ def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), I32:$Rt)),
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def: Pat<(add (mul I32:$Rs, u6_0ImmPred:$U6), u32_0ImmPred:$u6),
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(M4_mpyri_addi imm:$u6, IntRegs:$Rs, imm:$U6)>;
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def: Pat<(add (mul I32:$Rs, u6_0ImmPred:$U6),
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(HexagonCONST32 tglobaladdr:$global)),
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(M4_mpyri_addi tglobaladdr:$global, IntRegs:$Rs, imm:$U6)>;
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def: Pat<(add (mul I32:$Rs, I32:$Rt), u32_0ImmPred:$u6),
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(M4_mpyrr_addi imm:$u6, IntRegs:$Rs, IntRegs:$Rt)>;
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def: Pat<(add (mul I32:$Rs, I32:$Rt),
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(HexagonCONST32 tglobaladdr:$global)),
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(M4_mpyrr_addi tglobaladdr:$global, IntRegs:$Rs, IntRegs:$Rt)>;
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def: Pat<(add I32:$src1, (mul I32:$src3, u6_2ImmPred:$src2)),
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(M4_mpyri_addr_u2 IntRegs:$src1, imm:$src2, IntRegs:$src3)>;
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def: Pat<(add I32:$src1, (mul I32:$src3, u32_0ImmPred:$src2)),
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@ -2138,6 +2135,11 @@ let AddedComplexity = 30 in {
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def: Storea_pat<truncstorei8, I32, u32_0ImmPred, PS_storerbabs>;
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def: Storea_pat<truncstorei16, I32, u32_0ImmPred, PS_storerhabs>;
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def: Storea_pat<store, I32, u32_0ImmPred, PS_storeriabs>;
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def: Storea_pat<store, I64, u32_0ImmPred, PS_storerdabs>;
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def: Stoream_pat<truncstorei8, I64, u32_0ImmPred, LoReg, PS_storerbabs>;
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def: Stoream_pat<truncstorei16, I64, u32_0ImmPred, LoReg, PS_storerhabs>;
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def: Stoream_pat<truncstorei32, I64, u32_0ImmPred, LoReg, PS_storeriabs>;
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}
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let AddedComplexity = 30 in {
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@ -2146,6 +2148,19 @@ let AddedComplexity = 30 in {
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def: Loada_pat<zextloadi8, i32, u32_0ImmPred, PS_loadrubabs>;
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def: Loada_pat<sextloadi16, i32, u32_0ImmPred, PS_loadrhabs>;
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def: Loada_pat<zextloadi16, i32, u32_0ImmPred, PS_loadruhabs>;
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def: Loada_pat<load, i64, u32_0ImmPred, PS_loadrdabs>;
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def: Loadam_pat<extloadi8, i64, u32_0ImmPred, ToZext64, PS_loadrubabs>;
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def: Loadam_pat<sextloadi8, i64, u32_0ImmPred, ToSext64, PS_loadrbabs>;
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def: Loadam_pat<zextloadi8, i64, u32_0ImmPred, ToZext64, PS_loadrubabs>;
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def: Loadam_pat<extloadi16, i64, u32_0ImmPred, ToZext64, PS_loadruhabs>;
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def: Loadam_pat<sextloadi16, i64, u32_0ImmPred, ToSext64, PS_loadrhabs>;
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def: Loadam_pat<zextloadi16, i64, u32_0ImmPred, ToZext64, PS_loadruhabs>;
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def: Loadam_pat<extloadi32, i64, u32_0ImmPred, ToZext64, PS_loadriabs>;
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def: Loadam_pat<sextloadi32, i64, u32_0ImmPred, ToSext64, PS_loadriabs>;
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def: Loadam_pat<zextloadi32, i64, u32_0ImmPred, ToZext64, PS_loadriabs>;
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}
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// Indexed store word - global address.
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@ -2716,6 +2731,15 @@ def: Pat<(fneg F64:$Rs),
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(S2_togglebit_i (HiReg $Rs), 31), isub_hi,
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(i32 (LoReg $Rs)), isub_lo)>;
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def: Pat<(mul I64:$Rss, I64:$Rtt),
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(A2_combinew
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(M2_maci (M2_maci (HiReg (M2_dpmpyuu_s0 (LoReg $Rss), (LoReg $Rtt))),
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(LoReg $Rss),
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(HiReg $Rtt)),
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(LoReg $Rtt),
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(HiReg $Rss)),
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(LoReg (M2_dpmpyuu_s0 (LoReg $Rss), (LoReg $Rtt))))>;
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def alignedload : PatFrag<(ops node:$addr), (load $addr), [{
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return isAlignedMemNode(dyn_cast<MemSDNode>(N));
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}]>;
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