RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-25 04:02:41 +01:00
Code Issues Projects Releases Wiki Activity

[MachineCopyPropagation] Fix differences in code gen when compiling with -g

Browse Source 
Fixes bugs [[ https://bugs.llvm.org/show_bug.cgi?id=50580 | 50580 ]] and [[ https://bugs.llvm.org/show_bug.cgi?id=49446 | 49446  ]]

When compiling with -g "DBG_VALUE <reg>"  instructions are added in the MIR, if such a instruction is inserted between instructions that use <reg> then MachineCopyPropagation invalidates <reg> , this causes some copies  to not be propagated and causes differences in code generation (ex bugs 50580 and 49446 ).  DBG_VALUE instructions should be ignored  since they don't actually modify the register.

Reviewed By: lkail

Differential Revision: https://reviews.llvm.org/D104394
This commit is contained in:
Alexandru Octavian Butiu 2021-07-02 18:50:07 +08:00 committed by Kai Luo
parent a73a5b4199
commit 9690f39948
2 changed files with 42 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
lib/CodeGen/MachineCopyPropagation.cpp
View File

@ -870,12 +870,32 @@ void MachineCopyPropagation::BackwardCopyPropagateBlock(
if (MO.isDef()) if (MO.isDef())
Tracker.invalidateRegister(MO.getReg().asMCReg(), *TRI); Tracker.invalidateRegister(MO.getReg().asMCReg(), *TRI);
if (MO.readsReg()) if (MO.readsReg()) {
Tracker.invalidateRegister(MO.getReg().asMCReg(), *TRI); if (MO.isDebug()) {
// Check if the register in the debug instruction is utilized
// in a copy instruction, so we can update the debug info if the
// register is changed.
for (MCRegUnitIterator RUI(MO.getReg().asMCReg(), TRI); RUI.isValid();
++RUI) {
if (auto *Copy = Tracker.findCopyDefViaUnit(*RUI, *TRI)) {
CopyDbgUsers[Copy].insert(MI);
}
}
} else {
Tracker.invalidateRegister(MO.getReg().asMCReg(), *TRI);
}
}
} }
} }
for (auto *Copy : MaybeDeadCopies) { for (auto *Copy : MaybeDeadCopies) {
Register Src = Copy->getOperand(1).getReg();
Register Def = Copy->getOperand(0).getReg();
SmallVector<MachineInstr *> MaybeDeadDbgUsers(CopyDbgUsers[Copy].begin(),
CopyDbgUsers[Copy].end());
MRI->updateDbgUsersToReg(Src.asMCReg(), Def.asMCReg(), MaybeDeadDbgUsers);
Copy->eraseFromParent(); Copy->eraseFromParent();
++NumDeletes; ++NumDeletes;
} }

20
test/CodeGen/X86/machine-copy-dbgvalue.mir Normal file
View File

@ -0,0 +1,20 @@
# RUN: llc -mtriple=i686-- -run-pass machine-cp -verify-machineinstrs -o - %s | FileCheck %s
---
# Test that machine copy propagation ignores DBG_VALUE and DBL_VALUE_LIST and updates it.
# CHECK-LABEL: name: foo
# CHECK: bb.0:
# CHECK-NEXT: $rax = MOV64ri 31
# CHECK-NEXT: DBG_VALUE $rax
# CHECK-NEXT: DBG_VALUE_LIST 0, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_constu, 4, DW_OP_mul, DW_OP_plus, DW_OP_stack_value), $rax, 0, 0
# CHECK-NEXT: RETQ implicit killed $rax
name: foo
body: |
bb.0:
renamable $rcx = MOV64ri 31
DBG_VALUE $rcx, 0, 0, 0, 0
DBG_VALUE_LIST 0, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_constu, 4, DW_OP_mul, DW_OP_plus, DW_OP_stack_value), $rcx, 0, 0
$rax = COPY killed renamable $rcx
RETQ implicit killed $rax
...