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Intel syntax: Parse segment registers.

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llvm-svn: 148712
This commit is contained in:
Devang Patel 2012-01-23 18:31:58 +00:00
parent 6d71b145da
commit 9698de5bf3
2 changed files with 18 additions and 4 deletions
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20
lib/Target/X86/AsmParser/X86AsmParser.cpp
View File

@ -54,7 +54,7 @@ private:
X86Operand *ParseATTOperand();
X86Operand *ParseIntelOperand();
X86Operand *ParseIntelMemOperand();
X86Operand *ParseIntelBracExpression(unsigned Size);
X86Operand *ParseIntelBracExpression(unsigned SegReg, unsigned Size);
X86Operand *ParseMemOperand(unsigned SegReg, SMLoc StartLoc);
bool ParseDirectiveWord(unsigned Size, SMLoc L);
@ -593,8 +593,9 @@ static unsigned getIntelMemOperandSize(StringRef OpStr) {
return Size;
}
X86Operand *X86AsmParser::ParseIntelBracExpression(unsigned Size) {
unsigned SegReg = 0, BaseReg = 0, IndexReg = 0, Scale = 1;
X86Operand *X86AsmParser::ParseIntelBracExpression(unsigned SegReg,
unsigned Size) {
unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
SMLoc Start = Parser.getTok().getLoc(), End;
const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
@ -669,6 +670,7 @@ X86Operand *X86AsmParser::ParseIntelBracExpression(unsigned Size) {
X86Operand *X86AsmParser::ParseIntelMemOperand() {
const AsmToken &Tok = Parser.getTok();
SMLoc Start = Parser.getTok().getLoc(), End;
unsigned SegReg = 0;
unsigned Size = getIntelMemOperandSize(Tok.getString());
if (Size) {
@ -678,7 +680,17 @@ X86Operand *X86AsmParser::ParseIntelMemOperand() {
}
if (getLexer().is(AsmToken::LBrac))
return ParseIntelBracExpression(Size);
return ParseIntelBracExpression(SegReg, Size);
if (!ParseRegister(SegReg, Start, End)) {
// Handel SegReg : [ ... ]
if (getLexer().isNot(AsmToken::Colon))
return ErrorOperand(Start, "Expected ':' token!");
Parser.Lex(); // Eat :
if (getLexer().isNot(AsmToken::LBrac))
return ErrorOperand(Start, "Expected '[' token!");
return ParseIntelBracExpression(SegReg, Size);
}
const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
if (getParser().ParseExpression(Disp, End)) return 0;

2
test/MC/X86/intel-syntax.s
View File

@ -55,4 +55,6 @@ _main:
and rax, -257
// CHECK: fld %st(0)
fld ST(0)
// CHECK: movl %fs:(%rdi), %eax
mov EAX, DWORD PTR FS:[RDI]
ret