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[dfsan] Update store.ll test
This removes hard-coded shadow width references and adds more RUN lines to increase test coverage under different options (fast16 labels mode). Also, shortens the test by unifying common lines under both combine- and no-combine-ptr-label options. Reviewed By: stephan.yichao.zhao Differential Revision: https://reviews.llvm.org/D98227
This commit is contained in:
George Balatsouras
parent
fedce4ad20
commit
96bb976c88
@ -1,166 +1,141 @@
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; RUN: opt < %s -dfsan -dfsan-combine-pointer-labels-on-store=1 -S | FileCheck %s --check-prefix=COMBINE_PTR_LABEL
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; RUN: opt < %s -dfsan -dfsan-combine-pointer-labels-on-store=0 -S | FileCheck %s --check-prefix=NO_COMBINE_PTR_LABEL
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; RUN: opt < %s -dfsan -dfsan-combine-pointer-labels-on-store=1 -S | FileCheck %s --check-prefixes=CHECK,CHECK16,COMBINE_PTR_LABEL
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; RUN: opt < %s -dfsan -dfsan-combine-pointer-labels-on-store=0 -S | FileCheck %s --check-prefixes=CHECK,CHECK16,NO_COMBINE_PTR_LABEL
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; RUN: opt < %s -dfsan -dfsan-fast-16-labels -dfsan-combine-pointer-labels-on-store=1 -S | FileCheck %s --check-prefixes=CHECK,CHECK16,COMBINE_PTR_LABEL_FAST
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; RUN: opt < %s -dfsan -dfsan-fast-16-labels -dfsan-combine-pointer-labels-on-store=0 -S | FileCheck %s --check-prefixes=CHECK,CHECK16,NO_COMBINE_PTR_LABEL
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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define void @store0({} %v, {}* %p) {
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; COMBINE_PTR_LABEL: @"dfs$store0"
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; COMBINE_PTR_LABEL: store
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; COMBINE_PTR_LABEL-NOT: store
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; CHECK: @__dfsan_shadow_width_bits = weak_odr constant i32 [[#SBITS:]]
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; CHECK: @__dfsan_shadow_width_bytes = weak_odr constant i32 [[#SBYTES:]]
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; NO_COMBINE_PTR_LABEL: @"dfs$store0"
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; NO_COMBINE_PTR_LABEL: store
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; NO_COMBINE_PTR_LABEL-NOT: store
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define void @store0({} %v, {}* %p) {
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; CHECK-LABEL: @"dfs$store0"
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; CHECK: store {} %v, {}* %p
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; CHECK-NOT: store
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; CHECK: ret void
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store {} %v, {}* %p
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ret void
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}
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define void @store8(i8 %v, i8* %p) {
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; NO_COMBINE_PTR_LABEL: @"dfs$store8"
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; NO_COMBINE_PTR_LABEL: load i16, i16* {{.*}} @__dfsan_arg_tls
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; NO_COMBINE_PTR_LABEL: ptrtoint i8* {{.*}} i64
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; NO_COMBINE_PTR_LABEL: and i64
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; NO_COMBINE_PTR_LABEL: mul i64
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; NO_COMBINE_PTR_LABEL: inttoptr i64 {{.*}} i16*
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; NO_COMBINE_PTR_LABEL: getelementptr i16, i16*
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; NO_COMBINE_PTR_LABEL: store i16
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; NO_COMBINE_PTR_LABEL: store i8
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; CHECK-LABEL: @"dfs$store8"
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; CHECK: load i[[#SBITS]], i[[#SBITS]]* {{.*}} @__dfsan_arg_tls
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; COMBINE_PTR_LABEL: @"dfs$store8"
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; COMBINE_PTR_LABEL: load i16, i16*
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; COMBINE_PTR_LABEL: load i16, i16*
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; COMBINE_PTR_LABEL: icmp ne i16
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; COMBINE_PTR_LABEL: load i[[#SBITS]], i[[#SBITS]]* {{.*}} @__dfsan_arg_tls
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; COMBINE_PTR_LABEL: icmp ne i[[#SBITS]]
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; COMBINE_PTR_LABEL: call {{.*}} @__dfsan_union
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; COMBINE_PTR_LABEL: ptrtoint i8* {{.*}} i64
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; COMBINE_PTR_LABEL: and i64
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; COMBINE_PTR_LABEL: mul i64
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; COMBINE_PTR_LABEL: inttoptr i64 {{.*}} i16*
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; COMBINE_PTR_LABEL: getelementptr i16, i16*
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; COMBINE_PTR_LABEL: store i16
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; COMBINE_PTR_LABEL: store i8
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; COMM: When not in legacy mode, the three instructions above will
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; be replaced with the following:
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; COMBINE_PTR_LABEL_FAST: load i[[#SBITS]], i[[#SBITS]]* {{.*}} @__dfsan_arg_tls
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; COMBINE_PTR_LABEL_FAST: or i[[#SBITS]]
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; CHECK: ptrtoint i8* {{.*}} i64
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; CHECK-NEXT: and i64
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; CHECK16-NEXT: mul i64
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; CHECK-NEXT: inttoptr i64 {{.*}} i[[#SBITS]]*
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; CHECK-NEXT: getelementptr i[[#SBITS]], i[[#SBITS]]*
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; CHECK-NEXT: store i[[#SBITS]]
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; CHECK-NEXT: store i8 %v, i8* %p
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; CHECK-NEXT: ret void
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store i8 %v, i8* %p
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ret void
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}
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define void @store16(i16 %v, i16* %p) {
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; NO_COMBINE_PTR_LABEL: @"dfs$store16"
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; NO_COMBINE_PTR_LABEL: load i16, i16* {{.*}} @__dfsan_arg_tls
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; NO_COMBINE_PTR_LABEL: ptrtoint i16* {{.*}} i64
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; NO_COMBINE_PTR_LABEL: and i64
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; NO_COMBINE_PTR_LABEL: mul i64
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; NO_COMBINE_PTR_LABEL: inttoptr i64 {{.*}} i16*
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; NO_COMBINE_PTR_LABEL: getelementptr i16, i16*
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; NO_COMBINE_PTR_LABEL: store i16
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; NO_COMBINE_PTR_LABEL: getelementptr i16, i16*
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; NO_COMBINE_PTR_LABEL: store i16
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; NO_COMBINE_PTR_LABEL: store i16
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; CHECK-LABEL: @"dfs$store16"
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; CHECK: load i[[#SBITS]], i[[#SBITS]]* {{.*}} @__dfsan_arg_tls
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; COMBINE_PTR_LABEL: @"dfs$store16"
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; COMBINE_PTR_LABEL: load i16, i16* {{.*}} @__dfsan_arg_tls
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; COMBINE_PTR_LABEL: load i16, i16* {{.*}} @__dfsan_arg_tls
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; COMBINE_PTR_LABEL: icmp ne i16
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; COMBINE_PTR_LABEL: load i[[#SBITS]], i[[#SBITS]]* {{.*}} @__dfsan_arg_tls
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; COMBINE_PTR_LABEL: icmp ne i[[#SBITS]]
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; COMBINE_PTR_LABEL: call {{.*}} @__dfsan_union
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; COMBINE_PTR_LABEL: ptrtoint i16* {{.*}} i64
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; COMBINE_PTR_LABEL: and i64
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; COMBINE_PTR_LABEL: mul i64
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; COMBINE_PTR_LABEL: inttoptr i64 {{.*}} i16*
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; COMBINE_PTR_LABEL: getelementptr i16, i16*
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; COMBINE_PTR_LABEL: store i16
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; COMBINE_PTR_LABEL: getelementptr i16, i16*
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; COMBINE_PTR_LABEL: store i16
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; COMBINE_PTR_LABEL: store i16
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; COMM: When not in legacy mode, the three instructions above will
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; be replaced with the following:
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; COMBINE_PTR_LABEL_FAST: load i[[#SBITS]], i[[#SBITS]]* {{.*}} @__dfsan_arg_tls
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; COMBINE_PTR_LABEL_FAST: or i[[#SBITS]]
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; CHECK: ptrtoint i16* {{.*}} i64
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; CHECK-NEXT: and i64
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; CHECK16-NEXT: mul i64
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; CHECK-NEXT: inttoptr i64 {{.*}} i[[#SBITS]]*
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; CHECK-NEXT: getelementptr i[[#SBITS]], i[[#SBITS]]*
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; CHECK-NEXT: store i[[#SBITS]]
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; CHECK-NEXT: getelementptr i[[#SBITS]], i[[#SBITS]]*
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; CHECK-NEXT: store i[[#SBITS]]
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; CHECK-NEXT: store i16 %v, i16* %p
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; CHECK-NEXT: ret void
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store i16 %v, i16* %p
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ret void
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}
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define void @store32(i32 %v, i32* %p) {
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; NO_COMBINE_PTR_LABEL: @"dfs$store32"
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; NO_COMBINE_PTR_LABEL: load i16, i16* {{.*}} @__dfsan_arg_tls
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; NO_COMBINE_PTR_LABEL: ptrtoint i32* {{.*}} i64
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; NO_COMBINE_PTR_LABEL: and i64
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; NO_COMBINE_PTR_LABEL: mul i64
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; NO_COMBINE_PTR_LABEL: inttoptr i64 {{.*}} i16*
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; NO_COMBINE_PTR_LABEL: getelementptr i16, i16*
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; NO_COMBINE_PTR_LABEL: store i16
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; NO_COMBINE_PTR_LABEL: getelementptr i16, i16*
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; NO_COMBINE_PTR_LABEL: store i16
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; NO_COMBINE_PTR_LABEL: getelementptr i16, i16*
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; NO_COMBINE_PTR_LABEL: store i16
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; NO_COMBINE_PTR_LABEL: getelementptr i16, i16*
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; NO_COMBINE_PTR_LABEL: store i16
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; NO_COMBINE_PTR_LABEL: store i32
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; CHECK-LABEL: @"dfs$store32"
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; CHECK: load i[[#SBITS]], i[[#SBITS]]* {{.*}} @__dfsan_arg_tls
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; COMBINE_PTR_LABEL: @"dfs$store32"
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; COMBINE_PTR_LABEL: load i16, i16* {{.*}} @__dfsan_arg_tls
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; COMBINE_PTR_LABEL: load i16, i16* {{.*}} @__dfsan_arg_tls
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; COMBINE_PTR_LABEL: icmp ne i16
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; COMBINE_PTR_LABEL: load i[[#SBITS]], i[[#SBITS]]* {{.*}} @__dfsan_arg_tls
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; COMBINE_PTR_LABEL: icmp ne i[[#SBITS]]
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; COMBINE_PTR_LABEL: call {{.*}} @__dfsan_union
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; COMBINE_PTR_LABEL: ptrtoint i32* {{.*}} i64
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; COMBINE_PTR_LABEL: and i64
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; COMBINE_PTR_LABEL: mul i64
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; COMBINE_PTR_LABEL: inttoptr i64 {{.*}} i16*
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; COMBINE_PTR_LABEL: getelementptr i16, i16*
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; COMBINE_PTR_LABEL: store i16
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; COMBINE_PTR_LABEL: getelementptr i16, i16*
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; COMBINE_PTR_LABEL: store i16
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; COMBINE_PTR_LABEL: getelementptr i16, i16*
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; COMBINE_PTR_LABEL: store i16
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; COMBINE_PTR_LABEL: getelementptr i16, i16*
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; COMBINE_PTR_LABEL: store i16
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; COMBINE_PTR_LABEL: store i32
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; COMM: When not in legacy mode, the three instructions above will
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; be replaced with the following:
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; COMBINE_PTR_LABEL_FAST: load i[[#SBITS]], i[[#SBITS]]* {{.*}} @__dfsan_arg_tls
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; COMBINE_PTR_LABEL_FAST: or i[[#SBITS]]
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; CHECK: ptrtoint i32* {{.*}} i64
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; CHECK-NEXT: and i64
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; CHECK16-NEXT: mul i64
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; CHECK-NEXT: inttoptr i64 {{.*}} i[[#SBITS]]*
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; CHECK-NEXT: getelementptr i[[#SBITS]], i[[#SBITS]]*
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; CHECK-NEXT: store i[[#SBITS]]
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; CHECK-NEXT: getelementptr i[[#SBITS]], i[[#SBITS]]*
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; CHECK-NEXT: store i[[#SBITS]]
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; CHECK-NEXT: getelementptr i[[#SBITS]], i[[#SBITS]]*
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; CHECK-NEXT: store i[[#SBITS]]
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; CHECK-NEXT: getelementptr i[[#SBITS]], i[[#SBITS]]*
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; CHECK-NEXT: store i[[#SBITS]]
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; CHECK-NEXT: store i32 %v, i32* %p
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; CHECK-NEXT: ret void
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store i32 %v, i32* %p
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ret void
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}
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define void @store64(i64 %v, i64* %p) {
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; NO_COMBINE_PTR_LABEL: @"dfs$store64"
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; NO_COMBINE_PTR_LABEL: load i16, i16* {{.*}} @__dfsan_arg_tls
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; NO_COMBINE_PTR_LABEL: ptrtoint i64* {{.*}} i64
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; NO_COMBINE_PTR_LABEL: and i64
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; NO_COMBINE_PTR_LABEL: mul i64
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; NO_COMBINE_PTR_LABEL: inttoptr i64 {{.*}} i16*
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; NO_COMBINE_PTR_LABEL: insertelement {{.*}} i16
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; NO_COMBINE_PTR_LABEL: insertelement {{.*}} i16
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; NO_COMBINE_PTR_LABEL: insertelement {{.*}} i16
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; NO_COMBINE_PTR_LABEL: insertelement {{.*}} i16
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; NO_COMBINE_PTR_LABEL: insertelement {{.*}} i16
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; NO_COMBINE_PTR_LABEL: insertelement {{.*}} i16
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; NO_COMBINE_PTR_LABEL: insertelement {{.*}} i16
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; NO_COMBINE_PTR_LABEL: insertelement {{.*}} i16
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; NO_COMBINE_PTR_LABEL: bitcast i16* {{.*}} <8 x i16>*
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; NO_COMBINE_PTR_LABEL: store i64
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; CHECK-LABEL: @"dfs$store64"
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; CHECK: load i[[#SBITS]], i[[#SBITS]]* {{.*}} @__dfsan_arg_tls
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; COMBINE_PTR_LABEL: @"dfs$store64"
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; COMBINE_PTR_LABEL: load i16, i16* {{.*}} @__dfsan_arg_tls
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; COMBINE_PTR_LABEL: load i16, i16* {{.*}} @__dfsan_arg_tls
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; COMBINE_PTR_LABEL: icmp ne i16
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; COMBINE_PTR_LABEL: load i[[#SBITS]], i[[#SBITS]]* {{.*}} @__dfsan_arg_tls
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; COMBINE_PTR_LABEL: icmp ne i[[#SBITS]]
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; COMBINE_PTR_LABEL: call {{.*}} @__dfsan_union
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; COMBINE_PTR_LABEL: ptrtoint i64* {{.*}} i64
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; COMBINE_PTR_LABEL: and i64
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; COMBINE_PTR_LABEL: mul i64
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; COMBINE_PTR_LABEL: inttoptr i64 {{.*}} i16*
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; COMBINE_PTR_LABEL: insertelement {{.*}} i16
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; COMBINE_PTR_LABEL: insertelement {{.*}} i16
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; COMBINE_PTR_LABEL: insertelement {{.*}} i16
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; COMBINE_PTR_LABEL: insertelement {{.*}} i16
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; COMBINE_PTR_LABEL: insertelement {{.*}} i16
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; COMBINE_PTR_LABEL: insertelement {{.*}} i16
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; COMBINE_PTR_LABEL: insertelement {{.*}} i16
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; COMBINE_PTR_LABEL: insertelement {{.*}} i16
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; COMBINE_PTR_LABEL: bitcast i16* {{.*}} <8 x i16>*
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; COMBINE_PTR_LABEL: store <8 x i16>
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; COMBINE_PTR_LABEL: store i64
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; COMM: When not in legacy mode, the three instructions above will
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; be replaced with the following:
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; COMBINE_PTR_LABEL_FAST: load i[[#SBITS]], i[[#SBITS]]* {{.*}} @__dfsan_arg_tls
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; COMBINE_PTR_LABEL_FAST: or i[[#SBITS]]
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; CHECK: ptrtoint i64* {{.*}} i64
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; CHECK-NEXT: and i64
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; CHECK16-NEXT: mul i64
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; CHECK-NEXT: inttoptr i64 {{.*}} i[[#SBITS]]*
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; CHECK-COUNT-8: insertelement {{.*}} i[[#SBITS]]
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; CHECK-NEXT: bitcast i[[#SBITS]]* {{.*}} <8 x i[[#SBITS]]>*
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; CHECK-NEXT: getelementptr <8 x i[[#SBITS]]>
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; CHECK-NEXT: store <8 x i[[#SBITS]]>
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; CHECK-NEXT: store i64 %v, i64* %p
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; CHECK-NEXT: ret void
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store i64 %v, i64* %p
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ret void
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}
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define void @store_zero(i32* %p) {
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; NO_COMBINE_PTR_LABEL: store i64 0, i64* {{.*}}, align 2
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; CHECK-LABEL: @"dfs$store_zero"
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; NO_COMBINE_PTR_LABEL: bitcast i[[#SBITS]]* {{.*}} to i[[#mul(4, SBITS)]]*
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; NO_COMBINE_PTR_LABEL: store i[[#mul(4, SBITS)]] 0, i[[#mul(4, SBITS)]]* {{.*}}
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store i32 0, i32* %p
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ret void
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}
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}
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