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Fix PR7193: if sibling call address can take a register, make sure there are enough registers available by counting inreg arguments.

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llvm-svn: 105092
This commit is contained in:
Evan Cheng 2010-05-29 01:35:22 +00:00
parent 6631c8b9b7
commit 96bdf3e6f1
2 changed files with 34 additions and 0 deletions
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18
lib/Target/X86/X86ISelLowering.cpp
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@ -2427,6 +2427,24 @@ X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
} }
} }
} }
// If the tailcall address may be in a register, then make sure it's
// possible to register allocate for it. In 32-bit, the call address can
// only target EAX, EDX, or ECX since the tail call must be scheduled after
// callee-saved registers are restored. In 64-bit, it's RAX, RCX, RDX, RSI,
// RDI, R8, R9, R11.
if (!isa<GlobalAddressSDNode>(Callee) &&
!isa<ExternalSymbolSDNode>(Callee)) {
unsigned Limit = Subtarget->is64Bit() ? 8 : 3;
unsigned NumInRegs = 0;
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
CCValAssign &VA = ArgLocs[i];
if (VA.isRegLoc()) {
if (++NumInRegs == Limit)
return false;
}
}
}
} }
return true; return true;

16
test/CodeGen/X86/sibcall-3.ll Normal file
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@ -0,0 +1,16 @@
; RUN: llc < %s -mtriple=i386-unknown-unknown | FileCheck %s
; PR7193
define void @t1(i8* inreg %dst, i8* inreg %src, i8* inreg %len) nounwind {
; CHECK: t1:
; CHECK: call 0
tail call void null(i8* inreg %dst, i8* inreg %src, i8* inreg %len) nounwind
ret void
}
define void @t2(i8* inreg %dst, i8* inreg %src, i8* inreg %len) nounwind {
; CHECK: t2:
; CHECK: jmpl
tail call void null(i8* inreg %dst, i8* inreg %src) nounwind
ret void
}