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[AArch64][SVE] Add intrinsics for SVE2 cryptographic instructions
Summary: Implements the following SVE2 intrinsics: - @llvm.aarch64.sve.aesd - @llvm.aarch64.sve.aesimc - @llvm.aarch64.sve.aese - @llvm.aarch64.sve.aesmc - @llvm.aarch64.sve.rax1 - @llvm.aarch64.sve.sm4e - @llvm.aarch64.sve.sm4ekey Reviewers: sdesmalen, c-rhodes, dancgr, cameron.mcinally, efriedma, rengolin Reviewed By: sdesmalen Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, cfe-commits, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D74833
This commit is contained in:
Kerry McLaughlin
parent
4f8b0d2f56
commit
96fc6c2abc
@ -2022,4 +2022,37 @@ def int_aarch64_sve_bsl1n : AdvSIMD_3VectorArg_Intrinsic;
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def int_aarch64_sve_bsl2n : AdvSIMD_3VectorArg_Intrinsic;
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def int_aarch64_sve_nbsl : AdvSIMD_3VectorArg_Intrinsic;
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//
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// SVE2 - Optional AES, SHA-3 and SM4
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//
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def int_aarch64_sve_aesd : GCCBuiltin<"__builtin_sve_svaesd_u8">,
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Intrinsic<[llvm_nxv16i8_ty],
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[llvm_nxv16i8_ty, llvm_nxv16i8_ty],
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[IntrNoMem]>;
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def int_aarch64_sve_aesimc : GCCBuiltin<"__builtin_sve_svaesimc_u8">,
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Intrinsic<[llvm_nxv16i8_ty],
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[llvm_nxv16i8_ty],
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[IntrNoMem]>;
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def int_aarch64_sve_aese : GCCBuiltin<"__builtin_sve_svaese_u8">,
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Intrinsic<[llvm_nxv16i8_ty],
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[llvm_nxv16i8_ty, llvm_nxv16i8_ty],
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[IntrNoMem]>;
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def int_aarch64_sve_aesmc : GCCBuiltin<"__builtin_sve_svaesmc_u8">,
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Intrinsic<[llvm_nxv16i8_ty],
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[llvm_nxv16i8_ty],
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[IntrNoMem]>;
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def int_aarch64_sve_rax1 : GCCBuiltin<"__builtin_sve_svrax1_u64">,
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Intrinsic<[llvm_nxv2i64_ty],
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[llvm_nxv2i64_ty, llvm_nxv2i64_ty],
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[IntrNoMem]>;
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def int_aarch64_sve_sm4e : GCCBuiltin<"__builtin_sve_svsm4e_u32">,
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Intrinsic<[llvm_nxv4i32_ty],
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[llvm_nxv4i32_ty, llvm_nxv4i32_ty],
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[IntrNoMem]>;
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def int_aarch64_sve_sm4ekey : GCCBuiltin<"__builtin_sve_svsm4ekey_u32">,
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Intrinsic<[llvm_nxv4i32_ty],
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[llvm_nxv4i32_ty, llvm_nxv4i32_ty],
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[IntrNoMem]>;
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}
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@ -1917,12 +1917,12 @@ let Predicates = [HasSVE2] in {
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let Predicates = [HasSVE2AES] in {
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// SVE2 crypto destructive binary operations
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def AESE_ZZZ_B : sve2_crypto_des_bin_op<0b00, "aese", ZPR8>;
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def AESD_ZZZ_B : sve2_crypto_des_bin_op<0b01, "aesd", ZPR8>;
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defm AESE_ZZZ_B : sve2_crypto_des_bin_op<0b00, "aese", ZPR8, int_aarch64_sve_aese, nxv16i8>;
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defm AESD_ZZZ_B : sve2_crypto_des_bin_op<0b01, "aesd", ZPR8, int_aarch64_sve_aesd, nxv16i8>;
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// SVE2 crypto unary operations
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def AESMC_ZZ_B : sve2_crypto_unary_op<0b0, "aesmc">;
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def AESIMC_ZZ_B : sve2_crypto_unary_op<0b1, "aesimc">;
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defm AESMC_ZZ_B : sve2_crypto_unary_op<0b0, "aesmc", int_aarch64_sve_aesmc>;
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defm AESIMC_ZZ_B : sve2_crypto_unary_op<0b1, "aesimc", int_aarch64_sve_aesimc>;
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// PMULLB and PMULLT instructions which operate with 64-bit source and
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// 128-bit destination elements are enabled with crypto extensions, similar
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@ -1933,14 +1933,14 @@ let Predicates = [HasSVE2AES] in {
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let Predicates = [HasSVE2SM4] in {
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// SVE2 crypto constructive binary operations
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def SM4EKEY_ZZZ_S : sve2_crypto_cons_bin_op<0b0, "sm4ekey", ZPR32>;
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defm SM4EKEY_ZZZ_S : sve2_crypto_cons_bin_op<0b0, "sm4ekey", ZPR32, int_aarch64_sve_sm4ekey, nxv4i32>;
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// SVE2 crypto destructive binary operations
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def SM4E_ZZZ_S : sve2_crypto_des_bin_op<0b10, "sm4e", ZPR32>;
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defm SM4E_ZZZ_S : sve2_crypto_des_bin_op<0b10, "sm4e", ZPR32, int_aarch64_sve_sm4e, nxv4i32>;
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}
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let Predicates = [HasSVE2SHA3] in {
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// SVE2 crypto constructive binary operations
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def RAX1_ZZZ_D : sve2_crypto_cons_bin_op<0b1, "rax1", ZPR64>;
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defm RAX1_ZZZ_D : sve2_crypto_cons_bin_op<0b1, "rax1", ZPR64, int_aarch64_sve_rax1, nxv2i64>;
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}
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let Predicates = [HasSVE2BitPerm] in {
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@ -7101,6 +7101,12 @@ class sve2_crypto_cons_bin_op<bit opc, string asm, ZPRRegOp zprty>
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let Inst{4-0} = Zd;
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}
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multiclass sve2_crypto_cons_bin_op<bit opc, string asm, ZPRRegOp zprty,
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SDPatternOperator op, ValueType vt> {
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def NAME : sve2_crypto_cons_bin_op<opc, asm, zprty>;
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def : SVE_2_Op_Pat<vt, op, vt, vt, !cast<Instruction>(NAME)>;
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}
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class sve2_crypto_des_bin_op<bits<2> opc, string asm, ZPRRegOp zprty>
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: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, zprty:$Zm),
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asm, "\t$Zdn, $_Zdn, $Zm",
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@ -7118,8 +7124,14 @@ class sve2_crypto_des_bin_op<bits<2> opc, string asm, ZPRRegOp zprty>
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let Constraints = "$Zdn = $_Zdn";
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}
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class sve2_crypto_unary_op<bit opc, string asm>
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: I<(outs ZPR8:$Zdn), (ins ZPR8:$_Zdn),
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multiclass sve2_crypto_des_bin_op<bits<2> opc, string asm, ZPRRegOp zprty,
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SDPatternOperator op, ValueType vt> {
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def NAME : sve2_crypto_des_bin_op<opc, asm, zprty>;
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def : SVE_2_Op_Pat<vt, op, vt, vt, !cast<Instruction>(NAME)>;
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}
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class sve2_crypto_unary_op<bit opc, string asm, ZPRRegOp zprty>
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: I<(outs zprty:$Zdn), (ins zprty:$_Zdn),
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asm, "\t$Zdn, $_Zdn",
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"",
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[]>, Sched<[]> {
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@ -7132,6 +7144,11 @@ class sve2_crypto_unary_op<bit opc, string asm>
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let Constraints = "$Zdn = $_Zdn";
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}
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multiclass sve2_crypto_unary_op<bit opc, string asm, SDPatternOperator op> {
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def NAME : sve2_crypto_unary_op<opc, asm, ZPR8>;
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def : SVE_1_Op_Pat<nxv16i8, op, nxv16i8, !cast<Instruction>(NAME)>;
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}
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/// Addressing modes
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def am_sve_indexed_s4 :ComplexPattern<i64, 2, "SelectAddrModeIndexedSVE<-8,7>", [], [SDNPWantRoot]>;
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def am_sve_indexed_s6 :ComplexPattern<i64, 2, "SelectAddrModeIndexedSVE<-32,31>", [], [SDNPWantRoot]>;
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99
test/CodeGen/AArch64/sve2-intrinsics-crypto.ll
Normal file
99
test/CodeGen/AArch64/sve2-intrinsics-crypto.ll
Normal file
@ -0,0 +1,99 @@
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2-aes,+sve2-sha3,+sve2-sm4 -asm-verbose=0 < %s | FileCheck %s
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;
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; AESD
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;
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define <vscale x 16 x i8> @aesd_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
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; CHECK-LABEL: aesd_i8:
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; CHECK: aesd z0.b, z0.b, z1.b
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; CHECK-NEXT: ret
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%out = call <vscale x 16 x i8> @llvm.aarch64.sve.aesd(<vscale x 16 x i8> %a,
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<vscale x 16 x i8> %b)
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ret <vscale x 16 x i8> %out
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}
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;
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; AESIMC
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;
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define <vscale x 16 x i8> @aesimc_i8(<vscale x 16 x i8> %a) {
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; CHECK-LABEL: aesimc_i8:
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; CHECK: aesimc z0.b, z0.b
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; CHECK-NEXT: ret
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%out = call <vscale x 16 x i8> @llvm.aarch64.sve.aesimc(<vscale x 16 x i8> %a)
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ret <vscale x 16 x i8> %out
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}
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;
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; AESE
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;
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define <vscale x 16 x i8> @aese_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
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; CHECK-LABEL: aese_i8:
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; CHECK: aese z0.b, z0.b, z1.b
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; CHECK-NEXT: ret
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%out = call <vscale x 16 x i8> @llvm.aarch64.sve.aese(<vscale x 16 x i8> %a,
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<vscale x 16 x i8> %b)
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ret <vscale x 16 x i8> %out
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}
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;
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; AESMC
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;
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define <vscale x 16 x i8> @aesmc_i8(<vscale x 16 x i8> %a) {
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; CHECK-LABEL: aesmc_i8:
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; CHECK: aesmc z0.b, z0.b
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; CHECK-NEXT: ret
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%out = call <vscale x 16 x i8> @llvm.aarch64.sve.aesmc(<vscale x 16 x i8> %a)
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ret <vscale x 16 x i8> %out
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}
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;
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; RAX1
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;
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define <vscale x 2 x i64> @rax1_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
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; CHECK-LABEL: rax1_i64:
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; CHECK: rax1 z0.d, z0.d, z1.d
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; CHECK-NEXT: ret
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%out = call <vscale x 2 x i64> @llvm.aarch64.sve.rax1(<vscale x 2 x i64> %a,
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<vscale x 2 x i64> %b)
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ret <vscale x 2 x i64> %out
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}
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;
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; SM4E
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;
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define <vscale x 4 x i32> @sm4e_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
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; CHECK-LABEL: sm4e_i32:
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; CHECK: sm4e z0.s, z0.s, z1.s
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x i32> @llvm.aarch64.sve.sm4e(<vscale x 4 x i32> %a,
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<vscale x 4 x i32> %b)
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ret <vscale x 4 x i32> %out
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}
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;
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; SM4EKEY
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;
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define <vscale x 4 x i32> @sm4ekey_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
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; CHECK-LABEL: sm4ekey_i32:
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; CHECK: sm4ekey z0.s, z0.s, z1.s
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x i32> @llvm.aarch64.sve.sm4ekey(<vscale x 4 x i32> %a,
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<vscale x 4 x i32> %b)
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ret <vscale x 4 x i32> %out
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}
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declare <vscale x 16 x i8> @llvm.aarch64.sve.aesd(<vscale x 16 x i8>, <vscale x 16 x i8>)
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declare <vscale x 16 x i8> @llvm.aarch64.sve.aesimc(<vscale x 16 x i8>)
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declare <vscale x 16 x i8> @llvm.aarch64.sve.aese(<vscale x 16 x i8>, <vscale x 16 x i8>)
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declare <vscale x 16 x i8> @llvm.aarch64.sve.aesmc(<vscale x 16 x i8>)
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declare <vscale x 2 x i64> @llvm.aarch64.sve.rax1(<vscale x 2 x i64>, <vscale x 2 x i64>)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.sm4e(<vscale x 4 x i32>, <vscale x 4 x i32>)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.sm4ekey(<vscale x 4 x i32>, <vscale x 4 x i32>)
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