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[GVN] Don't perform scalar PRE on GEPs
Partial Redundancy Elimination of GEPs prevents CodeGenPrepare from sinking the addressing mode computation of memory instructions back to its uses. The problem comes from the insertion of PHIs, which confuse CGP and make it bail. I've autogenerated the check lines of an existing test and added a store instruction to demonstrate the motivation behind this change. The store is now using the gep instead of a phi. Differential Revision: https://reviews.llvm.org/D55009 llvm-svn: 348496
This commit is contained in:
Alexandros Lamprineas
parent
52ecd327f2
commit
9775e7e456
@ -2156,6 +2156,16 @@ bool GVN::performScalarPRE(Instruction *CurInst) {
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if (isa<CmpInst>(CurInst))
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return false;
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// Don't do PRE on GEPs. The inserted PHI would prevent CodeGenPrepare from
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// sinking the addressing mode computation back to its uses. Extending the
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// GEP's live range increases the register pressure, and therefore it can
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// introduce unnecessary spills.
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//
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// This doesn't prevent Load PRE. PHI translation will make the GEP available
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// to the load by moving it to the predecessor block if necessary.
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if (isa<GetElementPtrInst>(CurInst))
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return false;
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// We don't currently value number ANY inline asm calls.
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if (CallInst *CallI = dyn_cast<CallInst>(CurInst))
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if (CallI->isInlineAsm())
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@ -1,3 +1,4 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -basicaa -gvn -enable-load-pre -S | FileCheck %s
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; RUN: opt < %s -aa-pipeline=basic-aa -passes=gvn -enable-load-pre -S | FileCheck %s
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@ -6,11 +7,49 @@ target triple = "aarch64--linux-gnu"
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define double @foo(i32 %stat, i32 %i, double** %p) {
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; CHECK-LABEL: @foo(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: switch i32 [[STAT:%.*]], label [[SW_DEFAULT:%.*]] [
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; CHECK-NEXT: i32 0, label [[SW_BB:%.*]]
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; CHECK-NEXT: i32 1, label [[SW_BB]]
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; CHECK-NEXT: i32 2, label [[ENTRY_SW_BB2_CRIT_EDGE:%.*]]
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; CHECK-NEXT: ]
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; CHECK: entry.sw.bb2_crit_edge:
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; CHECK-NEXT: [[DOTPRE:%.*]] = load double*, double** [[P:%.*]], align 8
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; CHECK-NEXT: [[DOTPRE1:%.*]] = sext i32 [[I:%.*]] to i64
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; CHECK-NEXT: [[ARRAYIDX5_PHI_TRANS_INSERT:%.*]] = getelementptr inbounds double, double* [[DOTPRE]], i64 [[DOTPRE1]]
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; CHECK-NEXT: [[DOTPRE2:%.*]] = load double, double* [[ARRAYIDX5_PHI_TRANS_INSERT]], align 8
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; CHECK-NEXT: br label [[SW_BB2:%.*]]
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; CHECK: sw.bb:
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; CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[I]] to i64
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; CHECK-NEXT: [[TMP0:%.*]] = load double*, double** [[P]], align 8
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; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds double, double* [[TMP0]], i64 [[IDXPROM]]
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; CHECK-NEXT: [[TMP1:%.*]] = load double, double* [[ARRAYIDX1]], align 8
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; CHECK-NEXT: [[SUB:%.*]] = fsub double [[TMP1]], 1.000000e+00
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; CHECK-NEXT: [[CMP:%.*]] = fcmp olt double [[SUB]], 0.000000e+00
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; CHECK-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
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; CHECK: if.then:
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; CHECK-NEXT: br label [[RETURN:%.*]]
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; CHECK: if.end:
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; CHECK-NEXT: br label [[SW_BB2]]
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; CHECK: sw.bb2:
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; CHECK-NEXT: [[TMP2:%.*]] = phi double [ [[DOTPRE2]], [[ENTRY_SW_BB2_CRIT_EDGE]] ], [ [[TMP1]], [[IF_END]] ]
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; CHECK-NEXT: [[IDXPROM3_PRE_PHI:%.*]] = phi i64 [ [[DOTPRE1]], [[ENTRY_SW_BB2_CRIT_EDGE]] ], [ [[IDXPROM]], [[IF_END]] ]
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; CHECK-NEXT: [[TMP3:%.*]] = phi double* [ [[DOTPRE]], [[ENTRY_SW_BB2_CRIT_EDGE]] ], [ [[TMP0]], [[IF_END]] ]
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; CHECK-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds double, double* [[TMP3]], i64 [[IDXPROM3_PRE_PHI]]
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; CHECK-NEXT: [[SUB6:%.*]] = fsub double 3.000000e+00, [[TMP2]]
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; CHECK-NEXT: store double [[SUB6]], double* [[ARRAYIDX5]]
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; CHECK-NEXT: br label [[RETURN]]
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; CHECK: sw.default:
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; CHECK-NEXT: br label [[RETURN]]
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; CHECK: return:
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; CHECK-NEXT: [[RETVAL_0:%.*]] = phi double [ 0.000000e+00, [[SW_DEFAULT]] ], [ [[SUB6]], [[SW_BB2]] ], [ [[SUB]], [[IF_THEN]] ]
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; CHECK-NEXT: ret double [[RETVAL_0]]
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;
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entry:
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switch i32 %stat, label %sw.default [
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i32 0, label %sw.bb
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i32 1, label %sw.bb
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i32 2, label %sw.bb2
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i32 0, label %sw.bb
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i32 1, label %sw.bb
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i32 2, label %sw.bb2
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]
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sw.bb: ; preds = %entry, %entry
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@ -35,11 +74,8 @@ sw.bb2: ; preds = %if.end, %entry
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%2 = load double*, double** %arrayidx4, align 8
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%arrayidx5 = getelementptr inbounds double, double* %2, i64 %idxprom3
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%3 = load double, double* %arrayidx5, align 8
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; CHECK: sw.bb2:
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; CHECK-NOT: sext
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; CHECK: phi double [
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; CHECK-NOT: load
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%sub6 = fsub double 3.000000e+00, %3
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store double %sub6, double* %arrayidx5
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br label %return
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sw.default: ; preds = %entry
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@ -55,12 +91,24 @@ return: ; preds = %sw.default, %sw.bb2
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; actually processed. Make sure we can deal with the situation.
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define void @test_shortcut_safe(i1 %tst, i32 %p1, i32* %a) {
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; CHECK-LABEL: define void @test_shortcut_safe
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; CHECK: [[SEXT1:%.*]] = sext i32 %p1 to i64
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; CHECK: [[PHI1:%.*]] = phi i64 [ [[SEXT1]], {{%.*}} ], [ [[PHI2:%.*]], {{%.*}} ]
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; CHECK: [[SEXT2:%.*]] = sext i32 %p1 to i64
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; CHECK: [[PHI2]] = phi i64 [ [[SEXT2]], {{.*}} ], [ [[PHI1]], {{%.*}} ]
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; CHECK: getelementptr inbounds i32, i32* %a, i64 [[PHI2]]
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; CHECK-LABEL: @test_shortcut_safe(
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; CHECK-NEXT: br i1 [[TST:%.*]], label [[SEXT1:%.*]], label [[DOTPRE_DEST_CRIT_EDGE:%.*]]
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; CHECK: .pre.dest_crit_edge:
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; CHECK-NEXT: [[DOTPRE1:%.*]] = sext i32 [[P1:%.*]] to i64
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; CHECK-NEXT: br label [[PRE_DEST:%.*]]
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; CHECK: pre.dest:
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; CHECK-NEXT: [[DOTPRE_PRE_PHI:%.*]] = phi i64 [ [[DOTPRE1]], [[DOTPRE_DEST_CRIT_EDGE]] ], [ [[IDXPROM2_PRE_PHI:%.*]], [[SEXT_USE:%.*]] ]
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; CHECK-NEXT: br label [[SEXT_USE]]
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; CHECK: sext1:
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; CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[P1]] to i64
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; CHECK-NEXT: br label [[SEXT_USE]]
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; CHECK: sext.use:
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; CHECK-NEXT: [[IDXPROM2_PRE_PHI]] = phi i64 [ [[IDXPROM]], [[SEXT1]] ], [ [[DOTPRE_PRE_PHI]], [[PRE_DEST]] ]
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; CHECK-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds i32, i32* [[A:%.*]], i64 [[IDXPROM2_PRE_PHI]]
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; CHECK-NEXT: [[VAL:%.*]] = load i32, i32* [[ARRAYIDX3]], align 4
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; CHECK-NEXT: tail call void @g(i32 [[VAL]])
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; CHECK-NEXT: br label [[PRE_DEST]]
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;
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br i1 %tst, label %sext1, label %pre.dest
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