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[ARM] Replace hasNoSchedulingInfo with UnsupportedFeatures in the A57 schedule

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hasNoSchedulingInfo should be used for Pseudo's and other instructions
that are never expected to be scheduled. This removes the flag from new
ARM instructions, instead fixing the A57 schedule by marking the related
architecture features as unsupported.
This commit is contained in:
David Green 2020-04-27 09:19:06 +01:00
parent 4e339508d3
commit 9780cd1185
2 changed files with 3 additions and 22 deletions
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23
lib/Target/ARM/ARMInstrNEON.td
View File

@ -4838,15 +4838,6 @@ class VDOT<bit op6, bit op4, bit op23, RegisterClass RegTy, string Asm,
let Constraints = "$dst = $Vd";
}
class VUSDOT<bit op6, bit op4, bit op23, RegisterClass RegTy, string Asm,
string AsmTy, ValueType AccumTy, ValueType InputTy,
SDPatternOperator OpNode> :
VDOT<op6, op4, op23, RegTy, Asm, AsmTy, AccumTy, InputTy, OpNode> {
let hasNoSchedulingInfo = 1;
}
def VUDOTD : VDOT<0, 1, 0, DPR, "vudot", "u8", v2i32, v8i8, int_arm_neon_udot>;
def VSDOTD : VDOT<0, 0, 0, DPR, "vsdot", "s8", v2i32, v8i8, int_arm_neon_sdot>;
def VUDOTQ : VDOT<1, 1, 0, QPR, "vudot", "u8", v4i32, v16i8, int_arm_neon_udot>;
@ -4897,7 +4888,6 @@ let Predicates = [HasMatMulInt8] in {
(v16i8 QPR:$Vm)))]> {
let DecoderNamespace = "VFPV8";
let Constraints = "$dst = $Vd";
let hasNoSchedulingInfo = 1;
}
multiclass N3VMixedDotLane<bit Q, bit U, string Asm, string AsmTy, RegisterClass RegTy,
@ -4908,7 +4898,6 @@ let Predicates = [HasMatMulInt8] in {
(ins RegTy:$Vd, RegTy:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane), N3RegFrm,
NoItinerary, Asm, AsmTy, []> {
bit lane;
let hasNoSchedulingInfo = 1;
let Inst{5} = lane;
let AsmString = !strconcat(Asm, ".", AsmTy, "\t$Vd, $Vn, $Vm$lane");
let DecoderNamespace = "VFPV8";
@ -4939,8 +4928,8 @@ let Predicates = [HasMatMulInt8] in {
def VSMMLA : N3VMatMul<0, 0, "vsmmla", "s8", int_arm_neon_smmla>;
def VUMMLA : N3VMatMul<0, 1, "vummla", "u8", int_arm_neon_ummla>;
def VUSMMLA : N3VMatMul<1, 0, "vusmmla", "s8", int_arm_neon_usmmla>;
def VUSDOTD : VUSDOT<0, 0, 1, DPR, "vusdot", "s8", v2i32, v8i8, int_arm_neon_usdot>;
def VUSDOTQ : VUSDOT<1, 0, 1, QPR, "vusdot", "s8", v4i32, v16i8, int_arm_neon_usdot>;
def VUSDOTD : VDOT<0, 0, 1, DPR, "vusdot", "s8", v2i32, v8i8, int_arm_neon_usdot>;
def VUSDOTQ : VDOT<1, 0, 1, QPR, "vusdot", "s8", v4i32, v16i8, int_arm_neon_usdot>;
defm VUSDOTDI : N3VMixedDotLane<0, 0, "vusdot", "s8", DPR, v2i32, v8i8,
int_arm_neon_usdot, (v2i32 DPR_VFP2:$Vm)>;
@ -5295,7 +5284,6 @@ class VFMQ<string opc, string type, bits<2> S>
let Inst{3} = idx{0};
}
let hasNoSchedulingInfo = 1 in {
// op1 op2 op3
def VFMALD : N3VCP8F16Q0<"vfmal", DPR, SPR, SPR, 0b00, 0b10, 1>;
def VFMSLD : N3VCP8F16Q0<"vfmsl", DPR, SPR, SPR, 0b01, 0b10, 1>;
@ -5305,7 +5293,6 @@ def VFMALDI : VFMD<"vfmal", "f16", 0b00>;
def VFMSLDI : VFMD<"vfmsl", "f16", 0b01>;
def VFMALQI : VFMQ<"vfmal", "f16", 0b00>;
def VFMSLQI : VFMQ<"vfmsl", "f16", 0b01>;
}
} // HasNEON, HasFP16FML
@ -9001,7 +8988,6 @@ class BF16VDOT<bits<5> op27_23, bits<2> op21_20, bit op6,
dag oops, dag iops>
: N3Vnp<op27_23, op21_20, 0b1101, op6, 0, oops, iops,
N3RegFrm, IIC_VDOTPROD, "", "", []> {
let hasNoSchedulingInfo = 1;
let DecoderNamespace = "VFPV8";
}
@ -9042,7 +9028,6 @@ class BF16MM<bit Q, RegisterClass RegTy,
let Constraints = "$dst = $Vd";
let AsmString = !strconcat(opc, ".bf16", "\t$Vd, $Vn, $Vm");
let DecoderNamespace = "VFPV8";
let hasNoSchedulingInfo = 1;
}
def VMMLA : BF16MM<1, QPR, "vmmla">;
@ -9054,7 +9039,6 @@ class VBF16MALQ<bit T, string suffix>
[]> { // TODO: Add intrinsics
let Constraints = "$dst = $Vd";
let DecoderNamespace = "VFPV8";
let hasNoSchedulingInfo = 1;
}
def VBF16MALTQ: VBF16MALQ<1, "t">;
@ -9069,7 +9053,6 @@ multiclass VBF16MALQI<bit T, string suffix> {
let Inst{3} = idx{0};
let Constraints = "$dst = $Vd";
let DecoderNamespace = "VFPV8";
let hasNoSchedulingInfo = 1;
}
}
@ -9077,10 +9060,8 @@ multiclass VBF16MALQI<bit T, string suffix> {
defm VBF16MALTQI: VBF16MALQI<1, "t">;
defm VBF16MALBQI: VBF16MALQI<0, "b">;
let hasNoSchedulingInfo = 1 in {
def BF16_VCVT : N2V<0b11, 0b11, 0b01, 0b10, 0b01100, 1, 0,
(outs DPR:$Vd), (ins QPR:$Vm),
NoItinerary, "vcvt", "bf16.f32", "$Vd, $Vm", "", []>;
}
}
// End of BFloat16 instructions

2
lib/Target/ARM/ARMScheduleA57.td
View File

@ -96,7 +96,7 @@ def CortexA57Model : SchedMachineModel {
let FullInstRWOverlapCheck = 0;
let UnsupportedFeatures = [HasV8_1MMainline, HasMVEInt, HasMVEFloat,
HasFPRegsV8_1M];
HasFPRegsV8_1M, HasFP16FML, HasMatMulInt8, HasBF16];
}
//===----------------------------------------------------------------------===//