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X86ISD::SETCC (e.g. SETEr) produces a flag (so multiple SETCC can be
linked together). llvm-svn: 25247
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@ -161,8 +161,8 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
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if (X86ScalarSSE) {
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// Set up the FP register classes.
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addRegisterClass(MVT::f32, X86::V4F4RegisterClass);
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addRegisterClass(MVT::f64, X86::V2F8RegisterClass);
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addRegisterClass(MVT::f32, X86::FR32RegisterClass);
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addRegisterClass(MVT::f64, X86::FR64RegisterClass);
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// SSE has no load+extend ops
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setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
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@ -74,7 +74,8 @@ def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov,
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[SDNPOutFlag]>;
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def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
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[SDNPHasChain]>;
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def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC, []>;
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def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC,
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[SDNPOutFlag]>;
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def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
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[SDNPHasChain, SDNPOptInFlag]>;
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