From 97a493e7d722f76816f7bbda432b19878af72e20 Mon Sep 17 00:00:00 2001 From: Michael Kuperstein Date: Fri, 17 Jun 2016 20:21:17 +0000 Subject: [PATCH] [X86] Add missing AVX512 anyext patterns. Add AVX512 anyext patterns for i16 and i64, modeled on the existing i8 and i32 patterns. llvm-svn: 273038 --- lib/Target/X86/X86InstrAVX512.td | 8 +++++++ test/CodeGen/X86/pr28173.ll | 40 ++++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+) create mode 100644 test/CodeGen/X86/pr28173.ll diff --git a/lib/Target/X86/X86InstrAVX512.td b/lib/Target/X86/X86InstrAVX512.td index 5bd9dc7a527..4cee6181b84 100644 --- a/lib/Target/X86/X86InstrAVX512.td +++ b/lib/Target/X86/X86InstrAVX512.td @@ -2112,10 +2112,18 @@ let Predicates = [HasAVX512] in { def : Pat<(i64 (zext VK1:$src)), (AND64ri8 (SUBREG_TO_REG (i64 0), (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>; + def : Pat<(i64 (anyext VK1:$src)), + (SUBREG_TO_REG (i64 0), + (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit)>; + def : Pat<(i16 (zext VK1:$src)), (EXTRACT_SUBREG (AND32ri8 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_16bit)>; + def : Pat<(i16 (anyext VK1:$src)), + (EXTRACT_SUBREG + (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), + sub_16bit)>; } def : Pat<(v16i1 (scalar_to_vector VK1:$src)), (COPY_TO_REGCLASS VK1:$src, VK16)>; diff --git a/test/CodeGen/X86/pr28173.ll b/test/CodeGen/X86/pr28173.ll new file mode 100644 index 00000000000..81c10bb3757 --- /dev/null +++ b/test/CodeGen/X86/pr28173.ll @@ -0,0 +1,40 @@ +; RUN: llc -mattr=+avx512f < %s | FileCheck %s +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +; Note that the kmovs should really *not* appear in the output, this is an +; artifact of the current poor lowering. This is tracked by PR28175. + +; CHECK-LABEL: @foo64 +; CHECK: kmov +; CHECK: kmov +; CHECK: orq $-2, %rax +; CHECK: ret +define i64 @foo64(i1 zeroext %i, i32 %j) #0 { + br label %bb + +bb: + %z = zext i1 %i to i64 + %v = or i64 %z, -2 + br label %end + +end: + ret i64 %v +} + +; CHECK-LABEL: @foo16 +; CHECK: kmov +; CHECK: kmov +; CHECK: orl $65534, %eax +; CHECK: retq +define i16 @foo16(i1 zeroext %i, i32 %j) #0 { + br label %bb + +bb: + %z = zext i1 %i to i16 + %v = or i16 %z, -2 + br label %end + +end: + ret i16 %v +}