From 97ac53377a980782b20ef941605e4e6d1689fbf9 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Sat, 7 Oct 2017 17:57:22 +0000 Subject: [PATCH] [X86][SSE] Match bitcasted BUILD_VECTOR of constants for v2i64 shifts on 64-bit targets (PR34855) Extension to rL315155, generate constant shifts on 64-bits as well as 32-bits. llvm-svn: 315156 --- lib/Target/X86/X86ISelLowering.cpp | 4 ++-- test/CodeGen/X86/pr34855.ll | 6 ------ 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 6e45621bd96..9037a37f8b9 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -22150,9 +22150,9 @@ static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG, } } - // Special case in 32-bit mode, where i64 is expanded into high and low parts. + // Check cases (mainly 32-bit) where i64 is expanded into high and low parts. // TODO: Replace constant extraction with getTargetConstantBitsFromNode. - if (!Subtarget.is64Bit() && !Subtarget.hasXOP() && + if (!Subtarget.hasXOP() && (VT == MVT::v2i64 || (Subtarget.hasInt256() && VT == MVT::v4i64) || (Subtarget.hasAVX512() && VT == MVT::v8i64))) { diff --git a/test/CodeGen/X86/pr34855.ll b/test/CodeGen/X86/pr34855.ll index 286d7d2fe84..989c943ac03 100644 --- a/test/CodeGen/X86/pr34855.ll +++ b/test/CodeGen/X86/pr34855.ll @@ -18,12 +18,6 @@ define void @PR34855(<2 x i32> *%p0, <2 x i32> *%p1, <2 x i32> *%p2) { ; X64-NEXT: movslq (%rdi), %rax ; X64-NEXT: movq %rax, %xmm1 ; X64-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0] -; X64-NEXT: pxor %xmm0, %xmm0 -; X64-NEXT: movdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808] -; X64-NEXT: psrlq %xmm0, %xmm2 -; X64-NEXT: psrlq %xmm0, %xmm1 -; X64-NEXT: pxor %xmm2, %xmm1 -; X64-NEXT: psubq %xmm2, %xmm1 ; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,2,2,3] ; X64-NEXT: movq %xmm0, (%rdx) ; X64-NEXT: retq