mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2025-01-31 12:41:49 +01:00
fix function names; NFC
llvm-svn: 262367
This commit is contained in:
Sanjay Patel
parent
fc5944990a
commit
97d933d122
@ -23541,9 +23541,9 @@ bool X86TargetLowering::isGAPlusOffset(SDNode *N,
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/// Performs shuffle combines for 256-bit vectors.
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/// FIXME: This could be expanded to support 512 bit vectors as well.
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static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const X86Subtarget &Subtarget) {
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static SDValue combineShuffle256(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const X86Subtarget &Subtarget) {
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SDLoc dl(N);
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ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
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SDValue V1 = SVOp->getOperand(0);
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@ -24240,9 +24240,9 @@ static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
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}
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/// \brief Try to combine x86 target specific shuffles.
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static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const X86Subtarget &Subtarget) {
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static SDValue combineTargetShuffle(SDValue N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const X86Subtarget &Subtarget) {
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SDLoc DL(N);
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MVT VT = N.getSimpleValueType();
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SmallVector<int, 4> Mask;
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@ -24578,9 +24578,9 @@ static SDValue combineShuffleToAddSub(SDNode *N, const X86Subtarget &Subtarget,
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return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
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}
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static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const X86Subtarget &Subtarget) {
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static SDValue combineShuffle(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const X86Subtarget &Subtarget) {
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SDLoc dl(N);
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EVT VT = N->getValueType(0);
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@ -24598,7 +24598,7 @@ static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
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// Combine 256-bit vector shuffles. This is only profitable when in AVX mode
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if (TLI.isTypeLegal(VT) && Subtarget.hasFp256() && VT.is256BitVector() &&
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N->getOpcode() == ISD::VECTOR_SHUFFLE)
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return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
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return combineShuffle256(N, DAG, DCI, Subtarget);
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// During Type Legalization, when promoting illegal vector types,
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// the backend might introduce new shuffle dag nodes and bitcasts.
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@ -24668,7 +24668,7 @@ static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
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if (isTargetShuffle(N->getOpcode())) {
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if (SDValue Shuffle =
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PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget))
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combineTargetShuffle(SDValue(N, 0), DAG, DCI, Subtarget))
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return Shuffle;
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// Try recursively combining arbitrary sequences of x86 shuffle
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@ -24792,8 +24792,8 @@ static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
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EltNo);
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}
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static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG,
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const X86Subtarget &Subtarget) {
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static SDValue combineBitcast(SDNode *N, SelectionDAG &DAG,
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const X86Subtarget &Subtarget) {
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SDValue N0 = N->getOperand(0);
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EVT VT = N->getValueType(0);
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@ -24839,8 +24839,8 @@ static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG,
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/// bunch of shuffles and extracts into a somewhat faster sequence.
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/// For i686, the best sequence is apparently storing the value and loading
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/// scalars back, while for x64 we should use 64-bit extracts and shifts.
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static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI) {
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static SDValue combineExtractVectorElt(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI) {
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if (SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI))
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return NewOp;
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@ -25024,9 +25024,9 @@ transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
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}
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/// Do target-specific dag combines on SELECT and VSELECT nodes.
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static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const X86Subtarget &Subtarget) {
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static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const X86Subtarget &Subtarget) {
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SDLoc DL(N);
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SDValue Cond = N->getOperand(0);
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// Get the LHS/RHS of the select.
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@ -25715,9 +25715,9 @@ static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
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}
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/// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
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static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const X86Subtarget &Subtarget) {
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static SDValue combineCMov(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const X86Subtarget &Subtarget) {
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SDLoc DL(N);
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// If the flag operand isn't dead, don't touch this CMOV.
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@ -25926,8 +25926,8 @@ static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
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/// Optimize a single multiply with constant into two operations in order to
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/// implement it with two cheaper instructions, e.g. LEA + SHL, LEA + LEA.
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static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI) {
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static SDValue combineMul(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI) {
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// An imul is usually smaller than the alternative sequence.
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if (DAG.getMachineFunction().getFunction()->optForMinSize())
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return SDValue();
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@ -26012,7 +26012,7 @@ static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
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return SDValue();
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}
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static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
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static SDValue combineShiftLeft(SDNode *N, SelectionDAG &DAG) {
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SDValue N0 = N->getOperand(0);
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SDValue N1 = N->getOperand(1);
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ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
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@ -26072,7 +26072,7 @@ static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
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return SDValue();
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}
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static SDValue PerformSRACombine(SDNode *N, SelectionDAG &DAG) {
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static SDValue combineShiftRightAlgebraic(SDNode *N, SelectionDAG &DAG) {
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SDValue N0 = N->getOperand(0);
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SDValue N1 = N->getOperand(1);
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EVT VT = N0.getValueType();
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@ -26156,15 +26156,15 @@ static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
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return SDValue();
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}
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static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const X86Subtarget &Subtarget) {
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static SDValue combineShift(SDNode* N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const X86Subtarget &Subtarget) {
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if (N->getOpcode() == ISD::SHL)
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if (SDValue V = PerformSHLCombine(N, DAG))
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if (SDValue V = combineShiftLeft(N, DAG))
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return V;
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if (N->getOpcode() == ISD::SRA)
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if (SDValue V = PerformSRACombine(N, DAG))
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if (SDValue V = combineShiftRightAlgebraic(N, DAG))
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return V;
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// Try to fold this logical shift into a zero vector.
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@ -26178,9 +26178,9 @@ static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
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/// Recognize the distinctive (AND (setcc ...) (setcc ..)) where both setccs
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/// reference the same FP CMP, and rewrite for CMPEQSS and friends. Likewise for
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/// OR -> CMPNEQSS.
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static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const X86Subtarget &Subtarget) {
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static SDValue combineCompareEqual(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const X86Subtarget &Subtarget) {
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unsigned opcode;
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// SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
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@ -26404,7 +26404,7 @@ static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
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}
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}
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static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
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static SDValue combineVectorZext(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const X86Subtarget &Subtarget) {
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SDValue N0 = N->getOperand(0);
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@ -26529,16 +26529,16 @@ static SDValue convertIntLogicToFPLogic(SDNode *N, SelectionDAG &DAG,
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return SDValue();
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}
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static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const X86Subtarget &Subtarget) {
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static SDValue combineAnd(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const X86Subtarget &Subtarget) {
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if (DCI.isBeforeLegalizeOps())
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return SDValue();
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if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
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if (SDValue Zext = combineVectorZext(N, DAG, DCI, Subtarget))
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return Zext;
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if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
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if (SDValue R = combineCompareEqual(N, DAG, DCI, Subtarget))
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return R;
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if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
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@ -26693,13 +26693,13 @@ static SDValue combineLogicBlendIntoPBLENDV(SDNode *N, SelectionDAG &DAG,
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return DAG.getBitcast(VT, Mask);
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}
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static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const X86Subtarget &Subtarget) {
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static SDValue combineOr(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const X86Subtarget &Subtarget) {
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if (DCI.isBeforeLegalizeOps())
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return SDValue();
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if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
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if (SDValue R = combineCompareEqual(N, DAG, DCI, Subtarget))
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return R;
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if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
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@ -26781,7 +26781,7 @@ static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
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}
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// Generate NEG and CMOV for integer abs.
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static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
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static SDValue combineIntegerAbs(SDNode *N, SelectionDAG &DAG) {
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EVT VT = N->getValueType(0);
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// Since X86 does not have CMOV for 8-bit integer, we don't convert
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@ -26908,7 +26908,7 @@ static SDValue foldVectorXorShiftIntoCmp(SDNode *N, SelectionDAG &DAG,
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return DAG.getNode(X86ISD::PCMPGT, SDLoc(N), VT, Shift.getOperand(0), Ones);
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}
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static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
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static SDValue combineXor(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const X86Subtarget &Subtarget) {
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if (SDValue Cmp = foldVectorXorShiftIntoCmp(N, DAG, Subtarget))
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@ -26921,7 +26921,7 @@ static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
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return RV;
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if (Subtarget.hasCMov())
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if (SDValue RV = performIntegerAbsCombine(N, DAG))
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if (SDValue RV = combineIntegerAbs(N, DAG))
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return RV;
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if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
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@ -27048,9 +27048,9 @@ static SDValue detectAVGPattern(SDValue In, EVT VT, SelectionDAG &DAG,
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return SDValue();
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}
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static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const X86Subtarget &Subtarget) {
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static SDValue combineLoad(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const X86Subtarget &Subtarget) {
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LoadSDNode *Ld = cast<LoadSDNode>(N);
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EVT RegVT = Ld->getValueType(0);
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EVT MemVT = Ld->getMemoryVT();
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@ -27188,9 +27188,9 @@ reduceMaskedLoadToScalarLoad(MaskedLoadSDNode *ML, SelectionDAG &DAG,
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return DCI.CombineTo(ML, Insert, Load.getValue(1), true);
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}
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static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const X86Subtarget &Subtarget) {
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static SDValue combineMaskedLoad(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const X86Subtarget &Subtarget) {
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MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
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if (Mld->getExtensionType() == ISD::NON_EXTLOAD)
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return reduceMaskedLoadToScalarLoad(Mld, DAG, DCI);
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@ -27298,8 +27298,8 @@ static SDValue reduceMaskedStoreToScalarStore(MaskedStoreSDNode *MS,
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MS->isVolatile(), MS->isNonTemporal(), Alignment);
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}
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static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
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const X86Subtarget &Subtarget) {
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static SDValue combineMaskedStore(SDNode *N, SelectionDAG &DAG,
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const X86Subtarget &Subtarget) {
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MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
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if (!Mst->isTruncatingStore())
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return reduceMaskedStoreToScalarStore(Mst, DAG);
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@ -27387,8 +27387,8 @@ static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
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Mst->getMemOperand(), false);
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}
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static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
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const X86Subtarget &Subtarget) {
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static SDValue combineStore(SDNode *N, SelectionDAG &DAG,
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const X86Subtarget &Subtarget) {
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StoreSDNode *St = cast<StoreSDNode>(N);
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EVT VT = St->getValue().getValueType();
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EVT StVT = St->getMemoryVT();
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@ -27773,8 +27773,8 @@ static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
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}
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/// Do target-specific dag combines on floating-point adds/subs.
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static SDValue performFaddFsubCombine(SDNode *N, SelectionDAG &DAG,
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const X86Subtarget &Subtarget) {
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static SDValue combineFaddFsub(SDNode *N, SelectionDAG &DAG,
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const X86Subtarget &Subtarget) {
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EVT VT = N->getValueType(0);
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SDValue LHS = N->getOperand(0);
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SDValue RHS = N->getOperand(1);
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@ -27932,8 +27932,8 @@ static SDValue combineVectorTruncation(SDNode *N, SelectionDAG &DAG,
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return SDValue();
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}
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static SDValue PerformTRUNCATECombine(SDNode *N, SelectionDAG &DAG,
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const X86Subtarget &Subtarget) {
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static SDValue combineTruncate(SDNode *N, SelectionDAG &DAG,
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const X86Subtarget &Subtarget) {
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SDValue Src = N->getOperand(0);
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@ -27954,8 +27954,8 @@ static SDValue PerformTRUNCATECombine(SDNode *N, SelectionDAG &DAG,
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}
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/// Do target-specific dag combines on floating point negations.
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static SDValue PerformFNEGCombine(SDNode *N, SelectionDAG &DAG,
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const X86Subtarget &Subtarget) {
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static SDValue combineFneg(SDNode *N, SelectionDAG &DAG,
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const X86Subtarget &Subtarget) {
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EVT VT = N->getValueType(0);
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EVT SVT = VT.getScalarType();
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SDValue Arg = N->getOperand(0);
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@ -28022,8 +28022,8 @@ static SDValue lowerX86FPLogicOp(SDNode *N, SelectionDAG &DAG,
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return SDValue();
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}
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/// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
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static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG,
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const X86Subtarget &Subtarget) {
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static SDValue combineFOr(SDNode *N, SelectionDAG &DAG,
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const X86Subtarget &Subtarget) {
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assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
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// F[X]OR(0.0, x) -> x
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@ -28040,7 +28040,7 @@ static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG,
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}
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/// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
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static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
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static SDValue combineFMinFMax(SDNode *N, SelectionDAG &DAG) {
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assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
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// Only perform optimizations if UnsafeMath is used.
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@ -28060,8 +28060,8 @@ static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
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N->getOperand(0), N->getOperand(1));
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}
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static SDValue performFMinNumFMaxNumCombine(SDNode *N, SelectionDAG &DAG,
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const X86Subtarget &Subtarget) {
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static SDValue combineFMinNumFMaxNum(SDNode *N, SelectionDAG &DAG,
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const X86Subtarget &Subtarget) {
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if (Subtarget.useSoftFloat())
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return SDValue();
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@ -28117,8 +28117,8 @@ static SDValue performFMinNumFMaxNumCombine(SDNode *N, SelectionDAG &DAG,
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}
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/// Do target-specific dag combines on X86ISD::FAND nodes.
|
||||
static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG,
|
||||
const X86Subtarget &Subtarget) {
|
||||
static SDValue combineFAnd(SDNode *N, SelectionDAG &DAG,
|
||||
const X86Subtarget &Subtarget) {
|
||||
// FAND(0.0, x) -> 0.0
|
||||
if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
|
||||
if (C->getValueAPF().isPosZero())
|
||||
@ -28133,8 +28133,8 @@ static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG,
|
||||
}
|
||||
|
||||
/// Do target-specific dag combines on X86ISD::FANDN nodes
|
||||
static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG,
|
||||
const X86Subtarget &Subtarget) {
|
||||
static SDValue combineFAndn(SDNode *N, SelectionDAG &DAG,
|
||||
const X86Subtarget &Subtarget) {
|
||||
// FANDN(0.0, x) -> x
|
||||
if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
|
||||
if (C->getValueAPF().isPosZero())
|
||||
@ -28148,9 +28148,8 @@ static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG,
|
||||
return lowerX86FPLogicOp(N, DAG, Subtarget);
|
||||
}
|
||||
|
||||
static SDValue PerformBTCombine(SDNode *N,
|
||||
SelectionDAG &DAG,
|
||||
TargetLowering::DAGCombinerInfo &DCI) {
|
||||
static SDValue combineBT(SDNode *N, SelectionDAG &DAG,
|
||||
TargetLowering::DAGCombinerInfo &DCI) {
|
||||
// BT ignores high bits in the bit index operand.
|
||||
SDValue Op1 = N->getOperand(1);
|
||||
if (Op1.hasOneUse()) {
|
||||
@ -28167,7 +28166,7 @@ static SDValue PerformBTCombine(SDNode *N,
|
||||
return SDValue();
|
||||
}
|
||||
|
||||
static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
|
||||
static SDValue combineVZextMovl(SDNode *N, SelectionDAG &DAG) {
|
||||
SDValue Op = N->getOperand(0);
|
||||
if (Op.getOpcode() == ISD::BITCAST)
|
||||
Op = Op.getOperand(0);
|
||||
@ -28180,8 +28179,8 @@ static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
|
||||
return SDValue();
|
||||
}
|
||||
|
||||
static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
|
||||
const X86Subtarget &Subtarget) {
|
||||
static SDValue combineSignExtendInReg(SDNode *N, SelectionDAG &DAG,
|
||||
const X86Subtarget &Subtarget) {
|
||||
EVT VT = N->getValueType(0);
|
||||
if (!VT.isVector())
|
||||
return SDValue();
|
||||
@ -28372,9 +28371,9 @@ static SDValue combineToExtendVectorInReg(SDNode *N, SelectionDAG &DAG,
|
||||
return SDValue();
|
||||
}
|
||||
|
||||
static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
|
||||
TargetLowering::DAGCombinerInfo &DCI,
|
||||
const X86Subtarget &Subtarget) {
|
||||
static SDValue combineSext(SDNode *N, SelectionDAG &DAG,
|
||||
TargetLowering::DAGCombinerInfo &DCI,
|
||||
const X86Subtarget &Subtarget) {
|
||||
SDValue N0 = N->getOperand(0);
|
||||
EVT VT = N->getValueType(0);
|
||||
EVT InVT = N0.getValueType();
|
||||
@ -28406,8 +28405,8 @@ static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
|
||||
return SDValue();
|
||||
}
|
||||
|
||||
static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
|
||||
const X86Subtarget &Subtarget) {
|
||||
static SDValue combineFMA(SDNode *N, SelectionDAG &DAG,
|
||||
const X86Subtarget &Subtarget) {
|
||||
SDLoc dl(N);
|
||||
EVT VT = N->getValueType(0);
|
||||
|
||||
@ -28445,9 +28444,9 @@ static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
|
||||
return DAG.getNode(Opcode, dl, VT, A, B, C);
|
||||
}
|
||||
|
||||
static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
|
||||
TargetLowering::DAGCombinerInfo &DCI,
|
||||
const X86Subtarget &Subtarget) {
|
||||
static SDValue combineZext(SDNode *N, SelectionDAG &DAG,
|
||||
TargetLowering::DAGCombinerInfo &DCI,
|
||||
const X86Subtarget &Subtarget) {
|
||||
// (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
|
||||
// (and (i32 x86isd::setcc_carry), 1)
|
||||
// This eliminates the zext. This transformation is necessary because
|
||||
@ -28494,8 +28493,8 @@ static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
|
||||
|
||||
/// Optimize x == -y --> x+y == 0
|
||||
/// x != -y --> x+y != 0
|
||||
static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
|
||||
const X86Subtarget &Subtarget) {
|
||||
static SDValue combineSetCC(SDNode *N, SelectionDAG &DAG,
|
||||
const X86Subtarget &Subtarget) {
|
||||
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
|
||||
SDValue LHS = N->getOperand(0);
|
||||
SDValue RHS = N->getOperand(1);
|
||||
@ -28553,7 +28552,7 @@ static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
|
||||
return SDValue();
|
||||
}
|
||||
|
||||
static SDValue PerformGatherScatterCombine(SDNode *N, SelectionDAG &DAG) {
|
||||
static SDValue combineGatherScatter(SDNode *N, SelectionDAG &DAG) {
|
||||
SDLoc DL(N);
|
||||
// Gather and Scatter instructions use k-registers for masks. The type of
|
||||
// the masks is v*i1. So the mask will be truncated anyway.
|
||||
@ -28567,7 +28566,7 @@ static SDValue PerformGatherScatterCombine(SDNode *N, SelectionDAG &DAG) {
|
||||
return SDValue();
|
||||
}
|
||||
|
||||
// Helper function of PerformSETCCCombine. It is to materialize "setb reg"
|
||||
// Helper function of performSETCCCombine. It is to materialize "setb reg"
|
||||
// as "sbb reg,reg", since it can be extended without zext and produces
|
||||
// an all-ones bit which is more useful than 0/1 in some cases.
|
||||
static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
|
||||
@ -28586,9 +28585,9 @@ static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
|
||||
}
|
||||
|
||||
// Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
|
||||
static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
|
||||
TargetLowering::DAGCombinerInfo &DCI,
|
||||
const X86Subtarget &Subtarget) {
|
||||
static SDValue combineX86SetCC(SDNode *N, SelectionDAG &DAG,
|
||||
TargetLowering::DAGCombinerInfo &DCI,
|
||||
const X86Subtarget &Subtarget) {
|
||||
SDLoc DL(N);
|
||||
X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
|
||||
SDValue EFLAGS = N->getOperand(1);
|
||||
@ -28625,11 +28624,10 @@ static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
|
||||
return SDValue();
|
||||
}
|
||||
|
||||
// Optimize branch condition evaluation.
|
||||
//
|
||||
static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
|
||||
TargetLowering::DAGCombinerInfo &DCI,
|
||||
const X86Subtarget &Subtarget) {
|
||||
/// Optimize branch condition evaluation.
|
||||
static SDValue combineBrCond(SDNode *N, SelectionDAG &DAG,
|
||||
TargetLowering::DAGCombinerInfo &DCI,
|
||||
const X86Subtarget &Subtarget) {
|
||||
SDLoc DL(N);
|
||||
SDValue Chain = N->getOperand(0);
|
||||
SDValue Dest = N->getOperand(1);
|
||||
@ -28645,8 +28643,8 @@ static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
|
||||
return SDValue();
|
||||
}
|
||||
|
||||
static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
|
||||
SelectionDAG &DAG) {
|
||||
static SDValue combineVectorCompareAndMaskUnaryOp(SDNode *N,
|
||||
SelectionDAG &DAG) {
|
||||
// Take advantage of vector comparisons producing 0 or -1 in each lane to
|
||||
// optimize away operation when it's from a constant.
|
||||
//
|
||||
@ -28691,8 +28689,8 @@ static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
|
||||
return SDValue();
|
||||
}
|
||||
|
||||
static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
|
||||
const X86Subtarget &Subtarget) {
|
||||
static SDValue combineUIntToFP(SDNode *N, SelectionDAG &DAG,
|
||||
const X86Subtarget &Subtarget) {
|
||||
SDValue Op0 = N->getOperand(0);
|
||||
EVT VT = N->getValueType(0);
|
||||
EVT InVT = Op0.getValueType();
|
||||
@ -28716,11 +28714,11 @@ static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
|
||||
return SDValue();
|
||||
}
|
||||
|
||||
static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
|
||||
const X86Subtarget &Subtarget) {
|
||||
static SDValue combineSIntToFP(SDNode *N, SelectionDAG &DAG,
|
||||
const X86Subtarget &Subtarget) {
|
||||
// First try to optimize away the conversion entirely when it's
|
||||
// conditionally from a constant. Vectors only.
|
||||
if (SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG))
|
||||
if (SDValue Res = combineVectorCompareAndMaskUnaryOp(N, DAG))
|
||||
return Res;
|
||||
|
||||
// Now move on to more general possibilities.
|
||||
@ -28762,8 +28760,8 @@ static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
|
||||
}
|
||||
|
||||
// Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
|
||||
static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
|
||||
X86TargetLowering::DAGCombinerInfo &DCI) {
|
||||
static SDValue combineADC(SDNode *N, SelectionDAG &DAG,
|
||||
X86TargetLowering::DAGCombinerInfo &DCI) {
|
||||
// If the LHS and RHS of the ADC node are zero, then it can't overflow and
|
||||
// the result is either zero or one (depending on the input carry bit).
|
||||
// Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
|
||||
@ -28828,8 +28826,8 @@ static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
|
||||
DAG.getConstant(0, DL, OtherVal.getValueType()), NewCmp);
|
||||
}
|
||||
|
||||
static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
|
||||
const X86Subtarget &Subtarget) {
|
||||
static SDValue combineAdd(SDNode *N, SelectionDAG &DAG,
|
||||
const X86Subtarget &Subtarget) {
|
||||
EVT VT = N->getValueType(0);
|
||||
SDValue Op0 = N->getOperand(0);
|
||||
SDValue Op1 = N->getOperand(1);
|
||||
@ -28843,8 +28841,8 @@ static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
|
||||
return OptimizeConditionalInDecrement(N, DAG);
|
||||
}
|
||||
|
||||
static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
|
||||
const X86Subtarget &Subtarget) {
|
||||
static SDValue combineSub(SDNode *N, SelectionDAG &DAG,
|
||||
const X86Subtarget &Subtarget) {
|
||||
SDValue Op0 = N->getOperand(0);
|
||||
SDValue Op1 = N->getOperand(1);
|
||||
|
||||
@ -28876,9 +28874,9 @@ static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
|
||||
return OptimizeConditionalInDecrement(N, DAG);
|
||||
}
|
||||
|
||||
static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
|
||||
TargetLowering::DAGCombinerInfo &DCI,
|
||||
const X86Subtarget &Subtarget) {
|
||||
static SDValue combineVZext(SDNode *N, SelectionDAG &DAG,
|
||||
TargetLowering::DAGCombinerInfo &DCI,
|
||||
const X86Subtarget &Subtarget) {
|
||||
SDLoc DL(N);
|
||||
MVT VT = N->getSimpleValueType(0);
|
||||
SDValue Op = N->getOperand(0);
|
||||
@ -28940,7 +28938,7 @@ static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
|
||||
}
|
||||
|
||||
/// Canonicalize (LSUB p, 1) -> (LADD p, -1).
|
||||
static SDValue performLSUBCombine(SDNode *N, SelectionDAG &DAG,
|
||||
static SDValue combineLockSub(SDNode *N, SelectionDAG &DAG,
|
||||
const X86Subtarget &Subtarget) {
|
||||
SDValue Chain = N->getOperand(0);
|
||||
SDValue LHS = N->getOperand(1);
|
||||
@ -28964,54 +28962,50 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
|
||||
SelectionDAG &DAG = DCI.DAG;
|
||||
switch (N->getOpcode()) {
|
||||
default: break;
|
||||
case ISD::EXTRACT_VECTOR_ELT:
|
||||
return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
|
||||
case ISD::EXTRACT_VECTOR_ELT: return combineExtractVectorElt(N, DAG, DCI);
|
||||
case ISD::VSELECT:
|
||||
case ISD::SELECT:
|
||||
case X86ISD::SHRUNKBLEND:
|
||||
return PerformSELECTCombine(N, DAG, DCI, Subtarget);
|
||||
case ISD::BITCAST: return PerformBITCASTCombine(N, DAG, Subtarget);
|
||||
case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
|
||||
case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
|
||||
case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
|
||||
case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
|
||||
case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
|
||||
case X86ISD::SHRUNKBLEND: return combineSelect(N, DAG, DCI, Subtarget);
|
||||
case ISD::BITCAST: return combineBitcast(N, DAG, Subtarget);
|
||||
case X86ISD::CMOV: return combineCMov(N, DAG, DCI, Subtarget);
|
||||
case ISD::ADD: return combineAdd(N, DAG, Subtarget);
|
||||
case ISD::SUB: return combineSub(N, DAG, Subtarget);
|
||||
case X86ISD::ADC: return combineADC(N, DAG, DCI);
|
||||
case ISD::MUL: return combineMul(N, DAG, DCI);
|
||||
case ISD::SHL:
|
||||
case ISD::SRA:
|
||||
case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
|
||||
case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
|
||||
case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
|
||||
case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
|
||||
case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
|
||||
case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
|
||||
case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
|
||||
case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
|
||||
case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
|
||||
case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG, Subtarget);
|
||||
case ISD::SRL: return combineShift(N, DAG, DCI, Subtarget);
|
||||
case ISD::AND: return combineAnd(N, DAG, DCI, Subtarget);
|
||||
case ISD::OR: return combineOr(N, DAG, DCI, Subtarget);
|
||||
case ISD::XOR: return combineXor(N, DAG, DCI, Subtarget);
|
||||
case ISD::LOAD: return combineLoad(N, DAG, DCI, Subtarget);
|
||||
case ISD::MLOAD: return combineMaskedLoad(N, DAG, DCI, Subtarget);
|
||||
case ISD::STORE: return combineStore(N, DAG, Subtarget);
|
||||
case ISD::MSTORE: return combineMaskedStore(N, DAG, Subtarget);
|
||||
case ISD::SINT_TO_FP: return combineSIntToFP(N, DAG, Subtarget);
|
||||
case ISD::UINT_TO_FP: return combineUIntToFP(N, DAG, Subtarget);
|
||||
case ISD::FADD:
|
||||
case ISD::FSUB: return performFaddFsubCombine(N, DAG, Subtarget);
|
||||
case ISD::FNEG: return PerformFNEGCombine(N, DAG, Subtarget);
|
||||
case ISD::TRUNCATE: return PerformTRUNCATECombine(N, DAG, Subtarget);
|
||||
case ISD::FSUB: return combineFaddFsub(N, DAG, Subtarget);
|
||||
case ISD::FNEG: return combineFneg(N, DAG, Subtarget);
|
||||
case ISD::TRUNCATE: return combineTruncate(N, DAG, Subtarget);
|
||||
case X86ISD::FXOR:
|
||||
case X86ISD::FOR: return PerformFORCombine(N, DAG, Subtarget);
|
||||
case X86ISD::FOR: return combineFOr(N, DAG, Subtarget);
|
||||
case X86ISD::FMIN:
|
||||
case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
|
||||
case X86ISD::FMAX: return combineFMinFMax(N, DAG);
|
||||
case ISD::FMINNUM:
|
||||
case ISD::FMAXNUM: return performFMinNumFMaxNumCombine(N, DAG,
|
||||
Subtarget);
|
||||
case X86ISD::FAND: return PerformFANDCombine(N, DAG, Subtarget);
|
||||
case X86ISD::FANDN: return PerformFANDNCombine(N, DAG, Subtarget);
|
||||
case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
|
||||
case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
|
||||
case ISD::FMAXNUM: return combineFMinNumFMaxNum(N, DAG, Subtarget);
|
||||
case X86ISD::FAND: return combineFAnd(N, DAG, Subtarget);
|
||||
case X86ISD::FANDN: return combineFAndn(N, DAG, Subtarget);
|
||||
case X86ISD::BT: return combineBT(N, DAG, DCI);
|
||||
case X86ISD::VZEXT_MOVL: return combineVZextMovl(N, DAG);
|
||||
case ISD::ANY_EXTEND:
|
||||
case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
|
||||
case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
|
||||
case ISD::SIGN_EXTEND_INREG:
|
||||
return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
|
||||
case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
|
||||
case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
|
||||
case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
|
||||
case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
|
||||
case ISD::ZERO_EXTEND: return combineZext(N, DAG, DCI, Subtarget);
|
||||
case ISD::SIGN_EXTEND: return combineSext(N, DAG, DCI, Subtarget);
|
||||
case ISD::SIGN_EXTEND_INREG: return combineSignExtendInReg(N, DAG, Subtarget);
|
||||
case ISD::SETCC: return combineSetCC(N, DAG, Subtarget);
|
||||
case X86ISD::SETCC: return combineX86SetCC(N, DAG, DCI, Subtarget);
|
||||
case X86ISD::BRCOND: return combineBrCond(N, DAG, DCI, Subtarget);
|
||||
case X86ISD::VZEXT: return combineVZext(N, DAG, DCI, Subtarget);
|
||||
case X86ISD::SHUFP: // Handle all target specific shuffles
|
||||
case X86ISD::INSERTPS:
|
||||
case X86ISD::PALIGNR:
|
||||
@ -29031,11 +29025,11 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
|
||||
case X86ISD::MOVSD:
|
||||
case X86ISD::VPERMILPI:
|
||||
case X86ISD::VPERM2X128:
|
||||
case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
|
||||
case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
|
||||
case ISD::VECTOR_SHUFFLE: return combineShuffle(N, DAG, DCI,Subtarget);
|
||||
case ISD::FMA: return combineFMA(N, DAG, Subtarget);
|
||||
case ISD::MGATHER:
|
||||
case ISD::MSCATTER: return PerformGatherScatterCombine(N, DAG);
|
||||
case X86ISD::LSUB: return performLSUBCombine(N, DAG, Subtarget);
|
||||
case ISD::MSCATTER: return combineGatherScatter(N, DAG);
|
||||
case X86ISD::LSUB: return combineLockSub(N, DAG, Subtarget);
|
||||
}
|
||||
|
||||
return SDValue();
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user