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[RISCV] Support fixed-length INSERT_VECTOR_ELT
This patch enables support for lowering INSERT_VECTOR_ELT on fixed-length vector types. The strategy follows that for scalable vector types. This patch also includes a quick fix to prevent the compiler infinitely looping between lowering BUILD_VECTOR as VECTOR_SHUFFLE and back again. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D97698
This commit is contained in:
Fraser Cormack
parent
5fcbc5f0f5
commit
97dc903cfa
@ -554,6 +554,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
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}
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setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
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setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
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setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
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setOperationAction(ISD::ADD, VT, Custom);
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@ -610,6 +611,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
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setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
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setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
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setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
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setOperationAction(ISD::LOAD, VT, Custom);
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@ -1021,6 +1023,19 @@ getDefaultScalableVLOps(MVT VecVT, SDLoc DL, SelectionDAG &DAG,
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return getDefaultVLOps(VecVT, VecVT, DL, DAG, Subtarget);
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}
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// The state of RVV BUILD_VECTOR and VECTOR_SHUFFLE lowering is that very few
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// of either is (currently) supported. This can get us into an infinite loop
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// where we try to lower a BUILD_VECTOR as a VECTOR_SHUFFLE as a BUILD_VECTOR
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// as a ..., etc.
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// Until either (or both) of these can reliably lower any node, reporting that
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// we don't want to expand BUILD_VECTORs via VECTOR_SHUFFLEs at least breaks
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// the infinite loop. Note that this lowers BUILD_VECTOR through the stack,
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// which is not desirable.
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bool RISCVTargetLowering::shouldExpandBuildVectorWithShuffles(
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EVT VT, unsigned DefinedValues) const {
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return false;
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}
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static SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
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const RISCVSubtarget &Subtarget) {
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MVT VT = Op.getSimpleValueType();
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@ -2179,6 +2194,16 @@ SDValue RISCVTargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op,
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SDValue Val = Op.getOperand(1);
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SDValue Idx = Op.getOperand(2);
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MVT ContainerVT = VecVT;
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// If the operand is a fixed-length vector, convert to a scalable one.
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if (VecVT.isFixedLengthVector()) {
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ContainerVT = getContainerForFixedLengthVector(DAG, VecVT, Subtarget);
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Vec = convertToScalableVector(ContainerVT, Vec, DAG, Subtarget);
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}
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SDValue Mask, VL;
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std::tie(Mask, VL) = getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget);
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// Custom-legalize INSERT_VECTOR_ELT where XLEN>=SEW, so that the vector is
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// first slid down into position, the value is inserted into the first
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// position, and the vector is slid back up. We do this to simplify patterns.
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@ -2186,21 +2211,17 @@ SDValue RISCVTargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op,
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if (Subtarget.is64Bit() || Val.getValueType() != MVT::i64) {
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if (isNullConstant(Idx))
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return Op;
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SDValue Mask, VL;
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std::tie(Mask, VL) = getDefaultScalableVLOps(VecVT, DL, DAG, Subtarget);
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SDValue Slidedown = DAG.getNode(RISCVISD::VSLIDEDOWN_VL, DL, VecVT,
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DAG.getUNDEF(VecVT), Vec, Idx, Mask, VL);
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SDValue Slidedown =
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DAG.getNode(RISCVISD::VSLIDEDOWN_VL, DL, ContainerVT,
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DAG.getUNDEF(ContainerVT), Vec, Idx, Mask, VL);
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SDValue InsertElt0 =
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DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VecVT, Slidedown, Val,
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DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ContainerVT, Slidedown, Val,
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DAG.getConstant(0, DL, Subtarget.getXLenVT()));
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return DAG.getNode(RISCVISD::VSLIDEUP_VL, DL, VecVT, Vec, InsertElt0, Idx,
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Mask, VL);
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return DAG.getNode(RISCVISD::VSLIDEUP_VL, DL, ContainerVT, Vec, InsertElt0,
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Idx, Mask, VL);
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}
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if (!VecVT.isScalableVector())
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return SDValue();
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// Custom-legalize INSERT_VECTOR_ELT where XLEN<SEW, as the SEW element type
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// is illegal (currently only vXi64 RV32).
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// Since there is no easy way of getting a single element into a vector when
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@ -2212,17 +2233,21 @@ SDValue RISCVTargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op,
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// This essentially merges the original vector with the inserted element by
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// using a mask whose only set bit is that corresponding to the insert
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// index.
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SDValue SplattedVal = DAG.getSplatVector(VecVT, DL, Val);
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SDValue SplattedIdx = DAG.getNode(RISCVISD::SPLAT_VECTOR_I64, DL, VecVT, Idx);
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SDValue SplattedVal = DAG.getSplatVector(ContainerVT, DL, Val);
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SDValue SplattedIdx =
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DAG.getNode(RISCVISD::VMV_V_X_VL, DL, ContainerVT, Idx, VL);
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SDValue Mask, VL;
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std::tie(Mask, VL) = getDefaultScalableVLOps(VecVT, DL, DAG, Subtarget);
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SDValue VID = DAG.getNode(RISCVISD::VID_VL, DL, VecVT, Mask, VL);
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SDValue VID = DAG.getNode(RISCVISD::VID_VL, DL, ContainerVT, Mask, VL);
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auto SetCCVT =
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getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VecVT);
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SDValue SelectCond = DAG.getSetCC(DL, SetCCVT, VID, SplattedIdx, ISD::SETEQ);
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return DAG.getNode(ISD::VSELECT, DL, VecVT, SelectCond, SplattedVal, Vec);
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getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), ContainerVT);
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SDValue SelectCond =
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DAG.getNode(RISCVISD::SETCC_VL, DL, SetCCVT, VID, SplattedIdx,
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DAG.getCondCode(ISD::SETEQ), Mask, VL);
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SDValue Select = DAG.getNode(RISCVISD::VSELECT_VL, DL, ContainerVT,
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SelectCond, SplattedVal, Vec, VL);
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if (!VecVT.isFixedLengthVector())
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return Select;
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return convertFromScalableVector(VecVT, Select, DAG, Subtarget);
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}
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// Custom-lower EXTRACT_VECTOR_ELT operations to slide the vector down, then
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@ -243,6 +243,9 @@ public:
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bool ForCodeSize) const override;
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bool hasBitPreservingFPLogic(EVT VT) const override;
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bool
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shouldExpandBuildVectorWithShuffles(EVT VT,
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unsigned DefinedValues) const override;
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// Provide custom lowering hooks for some operations.
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SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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@ -8,88 +8,34 @@
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define void @insertelt_v4i64(<4 x i64>* %x, i64 %y) {
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; RV32-LABEL: insertelt_v4i64:
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; RV32: # %bb.0:
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; RV32-NEXT: addi sp, sp, -128
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; RV32-NEXT: .cfi_def_cfa_offset 128
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; RV32-NEXT: sw ra, 124(sp) # 4-byte Folded Spill
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; RV32-NEXT: sw s0, 120(sp) # 4-byte Folded Spill
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; RV32-NEXT: .cfi_offset ra, -4
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; RV32-NEXT: .cfi_offset s0, -8
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; RV32-NEXT: addi s0, sp, 128
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; RV32-NEXT: .cfi_def_cfa s0, 0
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; RV32-NEXT: andi sp, sp, -32
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; RV32-NEXT: sw a2, 32(sp)
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; RV32-NEXT: sw a1, 64(sp)
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; RV32-NEXT: vsetivli a1, 8, e32,m2,ta,mu
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; RV32-NEXT: vle32.v v26, (a0)
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; RV32-NEXT: vmv.x.s a1, v26
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; RV32-NEXT: sw a1, 0(sp)
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; RV32-NEXT: addi a1, sp, 32
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; RV32-NEXT: vle32.v v28, (a1)
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; RV32-NEXT: vmv.x.s a1, v28
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; RV32-NEXT: sw a1, 28(sp)
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; RV32-NEXT: addi a1, sp, 64
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; RV32-NEXT: vle32.v v28, (a1)
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; RV32-NEXT: vmv.x.s a1, v28
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; RV32-NEXT: sw a1, 24(sp)
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; RV32-NEXT: vsetivli a1, 1, e32,m2,ta,mu
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; RV32-NEXT: vslidedown.vi v28, v26, 5
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; RV32-NEXT: vmv.x.s a1, v28
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; RV32-NEXT: sw a1, 20(sp)
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; RV32-NEXT: vslidedown.vi v28, v26, 4
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; RV32-NEXT: vmv.x.s a1, v28
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; RV32-NEXT: sw a1, 16(sp)
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; RV32-NEXT: vslidedown.vi v28, v26, 3
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; RV32-NEXT: vmv.x.s a1, v28
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; RV32-NEXT: sw a1, 12(sp)
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; RV32-NEXT: vslidedown.vi v28, v26, 2
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; RV32-NEXT: vmv.x.s a1, v28
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; RV32-NEXT: sw a1, 8(sp)
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; RV32-NEXT: vslidedown.vi v26, v26, 1
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; RV32-NEXT: vmv.x.s a1, v26
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; RV32-NEXT: sw a1, 4(sp)
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; RV32-NEXT: vsetivli a1, 8, e32,m2,ta,mu
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; RV32-NEXT: vle32.v v26, (sp)
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; RV32-NEXT: vse32.v v26, (a0)
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; RV32-NEXT: addi sp, s0, -128
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; RV32-NEXT: lw s0, 120(sp) # 4-byte Folded Reload
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; RV32-NEXT: lw ra, 124(sp) # 4-byte Folded Reload
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; RV32-NEXT: addi sp, sp, 128
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; RV32-NEXT: vsetivli a3, 4, e64,m2,ta,mu
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; RV32-NEXT: vle64.v v26, (a0)
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; RV32-NEXT: vsetvli a3, zero, e64,m2,ta,mu
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; RV32-NEXT: vmv.v.x v28, a2
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; RV32-NEXT: addi a2, zero, 32
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; RV32-NEXT: vsll.vx v28, v28, a2
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; RV32-NEXT: vmv.v.x v30, a1
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; RV32-NEXT: vsll.vx v30, v30, a2
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; RV32-NEXT: vsrl.vx v30, v30, a2
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; RV32-NEXT: vor.vv v28, v30, v28
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; RV32-NEXT: vsetivli a1, 4, e64,m2,ta,mu
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; RV32-NEXT: vid.v v30
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; RV32-NEXT: vmseq.vi v0, v30, 3
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; RV32-NEXT: vmerge.vvm v26, v26, v28, v0
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; RV32-NEXT: vse64.v v26, (a0)
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; RV32-NEXT: ret
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;
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; RV64-LABEL: insertelt_v4i64:
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; RV64: # %bb.0:
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; RV64-NEXT: addi sp, sp, -96
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; RV64-NEXT: .cfi_def_cfa_offset 96
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; RV64-NEXT: sd ra, 88(sp) # 8-byte Folded Spill
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; RV64-NEXT: sd s0, 80(sp) # 8-byte Folded Spill
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; RV64-NEXT: .cfi_offset ra, -8
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; RV64-NEXT: .cfi_offset s0, -16
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; RV64-NEXT: addi s0, sp, 96
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; RV64-NEXT: .cfi_def_cfa s0, 0
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; RV64-NEXT: andi sp, sp, -32
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; RV64-NEXT: vsetivli a2, 4, e64,m2,ta,mu
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; RV64-NEXT: vle64.v v26, (a0)
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; RV64-NEXT: sd a1, 32(sp)
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; RV64-NEXT: vmv.x.s a1, v26
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; RV64-NEXT: sd a1, 0(sp)
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; RV64-NEXT: addi a1, sp, 32
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; RV64-NEXT: vle64.v v28, (a1)
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; RV64-NEXT: vmv.x.s a1, v28
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; RV64-NEXT: sd a1, 24(sp)
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; RV64-NEXT: vsetivli a1, 1, e64,m2,ta,mu
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; RV64-NEXT: vslidedown.vi v28, v26, 2
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; RV64-NEXT: vmv.x.s a1, v28
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; RV64-NEXT: sd a1, 16(sp)
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; RV64-NEXT: vslidedown.vi v26, v26, 1
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; RV64-NEXT: vmv.x.s a1, v26
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; RV64-NEXT: sd a1, 8(sp)
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; RV64-NEXT: vslidedown.vi v28, v26, 3
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; RV64-NEXT: vsetvli a2, zero, e64,m2,ta,mu
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; RV64-NEXT: vmv.s.x v28, a1
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; RV64-NEXT: vsetivli a1, 4, e64,m2,tu,mu
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; RV64-NEXT: vslideup.vi v26, v28, 3
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; RV64-NEXT: vsetivli a1, 4, e64,m2,ta,mu
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; RV64-NEXT: vle64.v v26, (sp)
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; RV64-NEXT: vse64.v v26, (a0)
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; RV64-NEXT: addi sp, s0, -96
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; RV64-NEXT: ld s0, 80(sp) # 8-byte Folded Reload
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; RV64-NEXT: ld ra, 88(sp) # 8-byte Folded Reload
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; RV64-NEXT: addi sp, sp, 96
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; RV64-NEXT: ret
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%a = load <4 x i64>, <4 x i64>* %x
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%b = insertelement <4 x i64> %a, i64 %y, i32 3
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@ -104,8 +50,39 @@ define void @insertelt_v4i64(<4 x i64>* %x, i64 %y) {
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define void @insertelt_v3i64(<3 x i64>* %x, i64 %y) {
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; RV32-LABEL: insertelt_v3i64:
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; RV32: # %bb.0:
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; RV32-NEXT: addi sp, sp, -16
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; RV32-NEXT: .cfi_def_cfa_offset 16
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; RV32-NEXT: addi a3, a0, 16
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; RV32-NEXT: vsetivli a4, 2, e32,m1,ta,mu
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; RV32-NEXT: vle32.v v25, (a3)
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; RV32-NEXT: vse32.v v25, (sp)
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; RV32-NEXT: vsetivli a3, 2, e64,m1,ta,mu
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; RV32-NEXT: vle64.v v26, (a0)
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; RV32-NEXT: vsetivli a3, 8, e32,m2,ta,mu
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; RV32-NEXT: vmv.v.i v28, 0
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; RV32-NEXT: vsetivli a3, 2, e64,m2,tu,mu
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; RV32-NEXT: vslideup.vi v28, v26, 0
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; RV32-NEXT: vsetivli a3, 4, e32,m1,ta,mu
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; RV32-NEXT: vle32.v v26, (sp)
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; RV32-NEXT: vsetivli a3, 4, e64,m2,tu,mu
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; RV32-NEXT: vslideup.vi v28, v26, 2
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; RV32-NEXT: vsetvli a3, zero, e64,m2,ta,mu
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; RV32-NEXT: vmv.v.x v26, a2
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; RV32-NEXT: addi a3, zero, 32
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; RV32-NEXT: vsll.vx v26, v26, a3
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; RV32-NEXT: vmv.v.x v30, a1
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; RV32-NEXT: vsll.vx v30, v30, a3
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; RV32-NEXT: vsrl.vx v30, v30, a3
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; RV32-NEXT: vor.vv v26, v30, v26
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; RV32-NEXT: vsetivli a3, 4, e64,m2,ta,mu
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; RV32-NEXT: vid.v v30
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; RV32-NEXT: vmseq.vi v0, v30, 2
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; RV32-NEXT: vmerge.vvm v26, v28, v26, v0
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; RV32-NEXT: vsetivli a3, 2, e64,m1,ta,mu
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; RV32-NEXT: vse64.v v26, (a0)
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; RV32-NEXT: sw a1, 16(a0)
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; RV32-NEXT: sw a2, 20(a0)
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; RV32-NEXT: addi sp, sp, 16
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; RV32-NEXT: ret
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;
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; RV64-LABEL: insertelt_v3i64:
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@ -117,3 +94,103 @@ define void @insertelt_v3i64(<3 x i64>* %x, i64 %y) {
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store <3 x i64> %b, <3 x i64>* %x
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ret void
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}
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define void @insertelt_v16i8(<16 x i8>* %x, i8 %y) {
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; RV32-LABEL: insertelt_v16i8:
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; RV32: # %bb.0:
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; RV32-NEXT: vsetivli a2, 16, e8,m1,ta,mu
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; RV32-NEXT: vle8.v v25, (a0)
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; RV32-NEXT: vslidedown.vi v26, v25, 14
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; RV32-NEXT: vsetvli a2, zero, e8,m1,ta,mu
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; RV32-NEXT: vmv.s.x v26, a1
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; RV32-NEXT: vsetivli a1, 16, e8,m1,tu,mu
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; RV32-NEXT: vslideup.vi v25, v26, 14
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; RV32-NEXT: vsetivli a1, 16, e8,m1,ta,mu
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; RV32-NEXT: vse8.v v25, (a0)
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; RV32-NEXT: ret
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;
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; RV64-LABEL: insertelt_v16i8:
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; RV64: # %bb.0:
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; RV64-NEXT: vsetivli a2, 16, e8,m1,ta,mu
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; RV64-NEXT: vle8.v v25, (a0)
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; RV64-NEXT: vslidedown.vi v26, v25, 14
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; RV64-NEXT: vsetvli a2, zero, e8,m1,ta,mu
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; RV64-NEXT: vmv.s.x v26, a1
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; RV64-NEXT: vsetivli a1, 16, e8,m1,tu,mu
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; RV64-NEXT: vslideup.vi v25, v26, 14
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; RV64-NEXT: vsetivli a1, 16, e8,m1,ta,mu
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; RV64-NEXT: vse8.v v25, (a0)
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; RV64-NEXT: ret
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%a = load <16 x i8>, <16 x i8>* %x
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%b = insertelement <16 x i8> %a, i8 %y, i32 14
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store <16 x i8> %b, <16 x i8>* %x
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ret void
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}
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define void @insertelt_v32i16(<32 x i16>* %x, i16 %y, i32 %idx) {
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; RV32-LABEL: insertelt_v32i16:
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; RV32: # %bb.0:
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; RV32-NEXT: addi a3, zero, 32
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; RV32-NEXT: vsetvli a4, a3, e16,m4,ta,mu
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; RV32-NEXT: vle16.v v28, (a0)
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; RV32-NEXT: vslidedown.vx v8, v28, a2
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; RV32-NEXT: vsetvli a4, zero, e16,m4,ta,mu
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; RV32-NEXT: vmv.s.x v8, a1
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; RV32-NEXT: vsetvli a1, a3, e16,m4,tu,mu
|
||||
; RV32-NEXT: vslideup.vx v28, v8, a2
|
||||
; RV32-NEXT: vsetvli a1, a3, e16,m4,ta,mu
|
||||
; RV32-NEXT: vse16.v v28, (a0)
|
||||
; RV32-NEXT: ret
|
||||
;
|
||||
; RV64-LABEL: insertelt_v32i16:
|
||||
; RV64: # %bb.0:
|
||||
; RV64-NEXT: addi a3, zero, 32
|
||||
; RV64-NEXT: vsetvli a4, a3, e16,m4,ta,mu
|
||||
; RV64-NEXT: vle16.v v28, (a0)
|
||||
; RV64-NEXT: sext.w a2, a2
|
||||
; RV64-NEXT: vslidedown.vx v8, v28, a2
|
||||
; RV64-NEXT: vsetvli a4, zero, e16,m4,ta,mu
|
||||
; RV64-NEXT: vmv.s.x v8, a1
|
||||
; RV64-NEXT: vsetvli a1, a3, e16,m4,tu,mu
|
||||
; RV64-NEXT: vslideup.vx v28, v8, a2
|
||||
; RV64-NEXT: vsetvli a1, a3, e16,m4,ta,mu
|
||||
; RV64-NEXT: vse16.v v28, (a0)
|
||||
; RV64-NEXT: ret
|
||||
%a = load <32 x i16>, <32 x i16>* %x
|
||||
%b = insertelement <32 x i16> %a, i16 %y, i32 %idx
|
||||
store <32 x i16> %b, <32 x i16>* %x
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @insertelt_v8f32(<8 x float>* %x, float %y, i32 %idx) {
|
||||
; RV32-LABEL: insertelt_v8f32:
|
||||
; RV32: # %bb.0:
|
||||
; RV32-NEXT: vsetivli a2, 8, e32,m2,ta,mu
|
||||
; RV32-NEXT: vle32.v v26, (a0)
|
||||
; RV32-NEXT: vslidedown.vx v28, v26, a1
|
||||
; RV32-NEXT: vsetvli a2, zero, e32,m2,ta,mu
|
||||
; RV32-NEXT: vfmv.s.f v28, fa0
|
||||
; RV32-NEXT: vsetivli a2, 8, e32,m2,tu,mu
|
||||
; RV32-NEXT: vslideup.vx v26, v28, a1
|
||||
; RV32-NEXT: vsetivli a1, 8, e32,m2,ta,mu
|
||||
; RV32-NEXT: vse32.v v26, (a0)
|
||||
; RV32-NEXT: ret
|
||||
;
|
||||
; RV64-LABEL: insertelt_v8f32:
|
||||
; RV64: # %bb.0:
|
||||
; RV64-NEXT: vsetivli a2, 8, e32,m2,ta,mu
|
||||
; RV64-NEXT: vle32.v v26, (a0)
|
||||
; RV64-NEXT: sext.w a1, a1
|
||||
; RV64-NEXT: vslidedown.vx v28, v26, a1
|
||||
; RV64-NEXT: vsetvli a2, zero, e32,m2,ta,mu
|
||||
; RV64-NEXT: vfmv.s.f v28, fa0
|
||||
; RV64-NEXT: vsetivli a2, 8, e32,m2,tu,mu
|
||||
; RV64-NEXT: vslideup.vx v26, v28, a1
|
||||
; RV64-NEXT: vsetivli a1, 8, e32,m2,ta,mu
|
||||
; RV64-NEXT: vse32.v v26, (a0)
|
||||
; RV64-NEXT: ret
|
||||
%a = load <8 x float>, <8 x float>* %x
|
||||
%b = insertelement <8 x float> %a, float %y, i32 %idx
|
||||
store <8 x float> %b, <8 x float>* %x
|
||||
ret void
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user