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Fix comment. Other formatting changes. No functionality changes.
llvm-svn: 57785
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0a9525febd
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@ -2207,7 +2207,7 @@ void SelectionDAGLowering::visitUIToFP(User &I) {
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}
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void SelectionDAGLowering::visitSIToFP(User &I){
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// UIToFP is never a no-op cast, no need to check
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// SIToFP is never a no-op cast, no need to check
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SDValue N = getValue(I.getOperand(0));
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MVT DestVT = TLI.getValueType(I.getType());
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setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
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@ -3079,6 +3079,7 @@ SelectionDAGLowering::visitLog2(CallInst &I) {
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void
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SelectionDAGLowering::visitLog10(CallInst &I) {
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SDValue result;
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if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
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LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
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SDValue Op = getValue(I.getOperand(1));
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@ -4221,13 +4222,13 @@ SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
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else if (NumZeroBits >= RegSize-9)
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isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
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else if (NumSignBits > RegSize-16)
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isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
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isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
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else if (NumZeroBits >= RegSize-17)
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isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
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isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
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else if (NumSignBits > RegSize-32)
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isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
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isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
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else if (NumZeroBits >= RegSize-33)
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isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
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isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
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if (FromVT != MVT::Other) {
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P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext,
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