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Revert "[AArch64] Simplify/refactor code to ease code review. NFC."
This reverts commit r245443, as it broke AArch64 test-suite tramp3d with an assert "Reg && "Null register has no regunits". llvm-svn: 245455
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@ -382,12 +382,10 @@ AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
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const MachineOperand &BaseRegOp =
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const MachineOperand &BaseRegOp =
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MergeForward ? getLdStBaseOp(Paired) : getLdStBaseOp(I);
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MergeForward ? getLdStBaseOp(Paired) : getLdStBaseOp(I);
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int Offset = getLdStOffsetOp(I).getImm();
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int PairedOffset = getLdStOffsetOp(Paired).getImm();
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// Which register is Rt and which is Rt2 depends on the offset order.
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// Which register is Rt and which is Rt2 depends on the offset order.
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MachineInstr *RtMI, *Rt2MI;
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MachineInstr *RtMI, *Rt2MI;
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if (Offset == PairedOffset + OffsetStride) {
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if (getLdStOffsetOp(I).getImm() ==
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getLdStOffsetOp(Paired).getImm() + OffsetStride) {
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RtMI = Paired;
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RtMI = Paired;
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Rt2MI = I;
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Rt2MI = I;
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// Here we swapped the assumption made for SExtIdx.
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// Here we swapped the assumption made for SExtIdx.
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@ -399,7 +397,7 @@ AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
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RtMI = I;
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RtMI = I;
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Rt2MI = Paired;
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Rt2MI = Paired;
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}
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}
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// Scale the immediate offset, if necessary.
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// Handle Unscaled
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int OffsetImm = getLdStOffsetOp(RtMI).getImm();
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int OffsetImm = getLdStOffsetOp(RtMI).getImm();
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if (IsUnscaled && EnableAArch64UnscaledMemOp)
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if (IsUnscaled && EnableAArch64UnscaledMemOp)
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OffsetImm /= OffsetStride;
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OffsetImm /= OffsetStride;
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@ -533,28 +531,6 @@ static bool mayAlias(MachineInstr *MIa,
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return false;
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return false;
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}
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}
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static bool canMergeOpc(unsigned Opc, unsigned PairOpc, LdStPairFlags &Flags) {
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bool CanMergeOpc = Opc == PairOpc;
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// Opcodes match nothing more to check.
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if (CanMergeOpc)
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return true;
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// Try to match a signed-extended load/store with a zero-extended load/store.
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Flags.setSExtIdx(-1);
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bool IsValidLdStrOpc;
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unsigned NonSExtOpc = getMatchingNonSExtOpcode(Opc, &IsValidLdStrOpc);
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assert(IsValidLdStrOpc &&
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"Given Opc should be a Load or Store with an immediate");
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// Opc will be the first instruction in the pair.
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CanMergeOpc = NonSExtOpc == getMatchingNonSExtOpcode(PairOpc);
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if (CanMergeOpc) {
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Flags.setSExtIdx(NonSExtOpc == (unsigned)Opc ? 1 : 0);
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return true;
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}
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return false;
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}
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/// findMatchingInsn - Scan the instructions looking for a load/store that can
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/// findMatchingInsn - Scan the instructions looking for a load/store that can
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/// be combined with the current instruction into a load/store pair.
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/// be combined with the current instruction into a load/store pair.
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MachineBasicBlock::iterator
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MachineBasicBlock::iterator
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@ -605,8 +581,19 @@ AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
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// Now that we know this is a real instruction, count it.
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// Now that we know this is a real instruction, count it.
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++Count;
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++Count;
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if (canMergeOpc(Opc, MI->getOpcode(), Flags) &&
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bool CanMergeOpc = Opc == MI->getOpcode();
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getLdStOffsetOp(MI).isImm()) {
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Flags.setSExtIdx(-1);
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if (!CanMergeOpc) {
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bool IsValidLdStrOpc;
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unsigned NonSExtOpc = getMatchingNonSExtOpcode(Opc, &IsValidLdStrOpc);
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assert(IsValidLdStrOpc &&
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"Given Opc should be a Load or Store with an immediate");
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// Opc will be the first instruction in the pair.
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Flags.setSExtIdx(NonSExtOpc == (unsigned)Opc ? 1 : 0);
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CanMergeOpc = NonSExtOpc == getMatchingNonSExtOpcode(MI->getOpcode());
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}
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if (CanMergeOpc && getLdStOffsetOp(MI).isImm()) {
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assert(MI->mayLoadOrStore() && "Expected memory operation.");
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assert(MI->mayLoadOrStore() && "Expected memory operation.");
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// If we've found another instruction with the same opcode, check to see
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// If we've found another instruction with the same opcode, check to see
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// if the base and offset are compatible with our starting instruction.
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// if the base and offset are compatible with our starting instruction.
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@ -630,9 +617,8 @@ AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
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return E;
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return E;
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// If the resultant immediate offset of merging these instructions
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// If the resultant immediate offset of merging these instructions
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// is out of range for a pairwise instruction, bail and keep looking.
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// is out of range for a pairwise instruction, bail and keep looking.
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assert (IsUnscaled == isUnscaledLdSt(MI) &&
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bool MIIsUnscaled = isUnscaledLdSt(MI);
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"Pair candidates should not be a mix of scaled and unscaled.");
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if (!inBoundsForPair(MIIsUnscaled, MinOffset, OffsetStride)) {
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if (!inBoundsForPair(IsUnscaled, MinOffset, OffsetStride)) {
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trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
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trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
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MemInsns.push_back(MI);
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MemInsns.push_back(MI);
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continue;
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continue;
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