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[mips] seq macro support
This patch adds the seq macro. This partially resolves PR/30381. Thanks to Sean Bruno for reporting the issue! Reviewers: zoran.jovanovic, vkalintiris, seanbruno Differential Revision: https://reviews.llvm.org/D24607 llvm-svn: 287573
This commit is contained in:
Simon Dardis
parent
d671a9d054
commit
984df218ce
@ -252,6 +252,12 @@ class MipsAsmParser : public MCTargetAsmParser {
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bool expandLoadStoreDMacro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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const MCSubtargetInfo *STI, bool IsLoad);
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bool expandSeq(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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const MCSubtargetInfo *STI);
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bool expandSeqI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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const MCSubtargetInfo *STI);
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bool reportParseError(Twine ErrorMsg);
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bool reportParseError(SMLoc Loc, Twine ErrorMsg);
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@ -2223,6 +2229,10 @@ MipsAsmParser::tryExpandInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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Inst.getOpcode() == Mips::LDMacro)
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? MER_Fail
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: MER_Success;
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case Mips::SEQMacro:
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return expandSeq(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
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case Mips::SEQIMacro:
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return expandSeqI(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
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}
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}
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@ -3915,6 +3925,85 @@ bool MipsAsmParser::expandLoadStoreDMacro(MCInst &Inst, SMLoc IDLoc,
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return false;
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}
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bool MipsAsmParser::expandSeq(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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const MCSubtargetInfo *STI) {
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warnIfNoMacro(IDLoc);
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MipsTargetStreamer &TOut = getTargetStreamer();
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if (Inst.getOperand(1).getReg() != Mips::ZERO &&
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Inst.getOperand(2).getReg() != Mips::ZERO) {
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TOut.emitRRR(Mips::XOR, Inst.getOperand(0).getReg(),
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Inst.getOperand(1).getReg(), Inst.getOperand(2).getReg(),
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IDLoc, STI);
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TOut.emitRRI(Mips::SLTiu, Inst.getOperand(0).getReg(),
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Inst.getOperand(0).getReg(), 1, IDLoc, STI);
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return false;
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}
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unsigned Reg = 0;
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if (Inst.getOperand(1).getReg() == Mips::ZERO) {
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Reg = Inst.getOperand(2).getReg();
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} else {
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Reg = Inst.getOperand(1).getReg();
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}
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TOut.emitRRI(Mips::SLTiu, Inst.getOperand(0).getReg(), Reg, 1, IDLoc, STI);
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return false;
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}
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bool MipsAsmParser::expandSeqI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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const MCSubtargetInfo *STI) {
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warnIfNoMacro(IDLoc);
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MipsTargetStreamer &TOut = getTargetStreamer();
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unsigned Opc;
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int64_t Imm = Inst.getOperand(2).getImm();
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unsigned Reg = Inst.getOperand(1).getReg();
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if (Imm == 0) {
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TOut.emitRRI(Mips::SLTiu, Inst.getOperand(0).getReg(),
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Inst.getOperand(1).getReg(), 1, IDLoc, STI);
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return false;
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} else {
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if (Reg == Mips::ZERO) {
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Warning(IDLoc, "comparison is always false");
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TOut.emitRRR(isGP64bit() ? Mips::DADDu : Mips::ADDu,
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Inst.getOperand(0).getReg(), Reg, Reg, IDLoc, STI);
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return false;
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}
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if (Imm > -0x8000 && Imm < 0) {
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Imm = -Imm;
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Opc = isGP64bit() ? Mips::DADDiu : Mips::ADDiu;
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} else {
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Opc = Mips::XORi;
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}
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}
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if (!isUInt<16>(Imm)) {
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unsigned ATReg = getATReg(IDLoc);
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if (!ATReg)
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return true;
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if (loadImmediate(Imm, ATReg, Mips::NoRegister, true, isGP64bit(), IDLoc,
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Out, STI))
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return true;
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TOut.emitRRR(Mips::XOR, Inst.getOperand(0).getReg(),
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Inst.getOperand(1).getReg(), ATReg, IDLoc, STI);
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TOut.emitRRI(Mips::SLTiu, Inst.getOperand(0).getReg(),
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Inst.getOperand(0).getReg(), 1, IDLoc, STI);
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return false;
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}
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TOut.emitRRI(Opc, Inst.getOperand(0).getReg(), Inst.getOperand(1).getReg(),
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Imm, IDLoc, STI);
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TOut.emitRRI(Mips::SLTiu, Inst.getOperand(0).getReg(),
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Inst.getOperand(0).getReg(), 1, IDLoc, STI);
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return false;
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}
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unsigned
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MipsAsmParser::checkEarlyTargetMatchPredicate(MCInst &Inst,
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const OperandVector &Operands) {
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@ -203,6 +203,8 @@ def InMips16Mode : Predicate<"Subtarget->inMips16Mode()">,
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AssemblerPredicate<"FeatureMips16">;
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def HasCnMips : Predicate<"Subtarget->hasCnMips()">,
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AssemblerPredicate<"FeatureCnMips">;
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def NotCnMips : Predicate<"!Subtarget->hasCnMips()">,
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AssemblerPredicate<"!FeatureCnMips">;
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def RelocNotPIC : Predicate<"!TM.isPositionIndependent()">;
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def RelocPIC : Predicate<"TM.isPositionIndependent()">;
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def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
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@ -335,6 +337,10 @@ class ASE_CNMIPS {
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list<Predicate> InsnPredicates = [HasCnMips];
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}
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class NOT_ASE_CNMIPS {
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list<Predicate> InsnPredicates = [NotCnMips];
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}
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class ASE_MIPS64_CNMIPS {
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list<Predicate> InsnPredicates = [HasMips64, HasCnMips];
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}
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@ -2260,6 +2266,21 @@ def : MipsInstAlias<"dror $rd, $imm",
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def ABSMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rs),
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"abs\t$rd, $rs">;
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def SEQMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
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(ins GPR32Opnd:$rs, GPR32Opnd:$rt),
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"seq $rd, $rs, $rt">, NOT_ASE_CNMIPS;
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def : MipsInstAlias<"seq $rd, $rs",
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(SEQMacro GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>,
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NOT_ASE_CNMIPS;
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def SEQIMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
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(ins GPR32Opnd:$rs, simm32_relaxed:$imm),
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"seq $rd, $rs, $imm">, NOT_ASE_CNMIPS;
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def : MipsInstAlias<"seq $rd, $imm",
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(SEQIMacro GPR32Opnd:$rd, GPR32Opnd:$rd, simm32:$imm), 0>,
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NOT_ASE_CNMIPS;
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//===----------------------------------------------------------------------===//
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// Instruction aliases
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//===----------------------------------------------------------------------===//
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52
test/MC/Mips/macro-seq.s
Normal file
52
test/MC/Mips/macro-seq.s
Normal file
@ -0,0 +1,52 @@
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# RUN: llvm-mc -arch=mips -mcpu=mips1 < %s | FileCheck --check-prefixes=ALL,MIPS32 %s
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# RUN: llvm-mc -arch=mips -mcpu=mips64 < %s | FileCheck --check-prefixes=ALL,MIPS64 %s
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# ALL: .text
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seq $2, $11, $0
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# ALL: sltiu $2, $11, 1
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seq $2, $0, $11
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# ALL: sltiu $2, $11, 1
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seq $2, $0, $0
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# ALL: sltiu $2, $zero, 1
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seq $2, $11, $12
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# ALL: xor $2, $11, $12
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# ALL: sltiu $2, $2, 1
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seq $2, $11, 45
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# ALL: xori $2, $11, 45
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seq $2, $12, 0x76666
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# ALL: lui $1, 7
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# ALL: ori $1, $1, 26214
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# ALL: xor $2, $12, $1
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# ALL: sltiu $2, $2, 1
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seq $2, $3
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# ALL: xor $2, $2, $3
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# ALL: sltiu $2, $2, 1
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seq $2, 0x8888
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# ALL: xori $2, $2, 34952
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# ALL: sltiu $2, $2, 1
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seq $2, $3, -1546
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# MIPS32: addiu $2, $3, 1546
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# MIPS64: daddiu $2, $3, 1546
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# ALL: sltiu $2, $2, 1
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seq $2, -7546
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# MIPS32: addiu $2, $2, 7546
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# MIPS64: daddiu $2, $2, 7546
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# ALL: sltiu $2, $2, 1
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seq $4, $5, -66666
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# ALL: lui $1, 65534
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# ALL: ori $1, $1, 64406
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# ALL: xor $4, $5, $1
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# ALL: sltiu $4, $4, 1
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seq $4, $5, -2147483648
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# ALL: lui $1, 32768
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# ALL: xor $4, $5, $1
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# ALL: sltiu $4, $4, 1
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seq $4, -2147483648
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# ALL: lui $1, 32768
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# ALL: xor $4, $4, $1
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# ALL: sltiu $4, $4, 1
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seq $4, $5, 0
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# ALL: sltiu $4, $5, 1
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seq $4, $zero, 1
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# MIPS32: move $4, $zero
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# MIPS64: daddu $4, $zero, $zero
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