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More consistent thumb1 asm printing.

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llvm-svn: 89328
This commit is contained in:
Evan Cheng 2009-11-19 06:57:41 +00:00
parent c2e359a418
commit 987b8c3d9a
8 changed files with 33 additions and 17 deletions
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25
lib/Target/ARM/ARMInstrThumb.td
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@ -66,6 +66,11 @@ def thumb_immshifted_shamt : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(V, MVT::i32);
}]>;
// Scaled 4 immediate.
def t_imm_s4 : Operand<i32> {
let PrintMethod = "printThumbS4ImmOperand";
}
// Define Thumb specific addressing modes.
// t_addrmode_rr := reg + reg
@ -134,20 +139,20 @@ def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr,
[(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>;
// PC relative add.
def tADDrPCi : T1I<(outs tGPR:$dst), (ins i32imm:$rhs), IIC_iALUi,
"add\t$dst, pc, $rhs * 4", []>;
def tADDrPCi : T1I<(outs tGPR:$dst), (ins t_imm_s4:$rhs), IIC_iALUi,
"add\t$dst, pc, $rhs", []>;
// ADD rd, sp, #imm8
def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, i32imm:$rhs), IIC_iALUi,
"add\t$dst, $sp, $rhs * 4", []>;
def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs), IIC_iALUi,
"add\t$dst, $sp, $rhs", []>;
// ADD sp, sp, #imm7
def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iALUi,
"add\t$dst, $rhs * 4", []>;
def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
"add\t$dst, $rhs", []>;
// SUB sp, sp, #imm7
def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iALUi,
"sub\t$dst, $rhs * 4", []>;
def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
"sub\t$dst, $rhs", []>;
// ADD rm, sp
def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
@ -159,8 +164,8 @@ def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
// Pseudo instruction that will expand into a tSUBspi + a copy.
let usesCustomInserter = 1 in { // Expanded after instruction selection.
def tSUBspi_ : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
NoItinerary, "@ sub\t$dst, $rhs * 4", []>;
def tSUBspi_ : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs),
NoItinerary, "@ sub\t$dst, $rhs", []>;
def tADDspr_ : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
NoItinerary, "@ add\t$dst, $rhs", []>;

5
lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
View File

@ -110,6 +110,7 @@ namespace {
const char *Modifier = 0);
void printBitfieldInvMaskImmOperand (const MachineInstr *MI, int OpNum);
void printThumbS4ImmOperand(const MachineInstr *MI, int OpNum);
void printThumbITMask(const MachineInstr *MI, int OpNum);
void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNum);
void printThumbAddrModeRI5Operand(const MachineInstr *MI, int OpNum,
@ -674,6 +675,10 @@ ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op) {
//===--------------------------------------------------------------------===//
void ARMAsmPrinter::printThumbS4ImmOperand(const MachineInstr *MI, int Op) {
O << "#" << MI->getOperand(Op).getImm() * 4;
}
void
ARMAsmPrinter::printThumbITMask(const MachineInstr *MI, int Op) {
// (3 - the number of trailing zeros) is the number of then / else.

5
lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp
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@ -351,3 +351,8 @@ void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum) {
// FIXME: remove this.
abort();
}
void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum) {
// FIXME: remove this.
abort();
}

1
lib/Target/ARM/AsmPrinter/ARMInstPrinter.h
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@ -53,6 +53,7 @@ public:
void printBitfieldInvMaskImmOperand(const MCInst *MI, unsigned OpNum);
void printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum);
void printThumbITMask(const MCInst *MI, unsigned OpNum) {}
void printThumbAddrModeRROperand(const MCInst *MI, unsigned OpNum) {}
void printThumbAddrModeRI5Operand(const MCInst *MI, unsigned OpNum,

2
test/CodeGen/Thumb/pop.ll
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@ -4,7 +4,7 @@
define arm_apcscc void @t(i8* %a, ...) nounwind {
; CHECK: t:
; CHECK: pop {r3}
; CHECK-NEXT: add sp, #3 * 4
; CHECK-NEXT: add sp, #12
; CHECK-NEXT: bx r3
entry:
%a.addr = alloca i8*

2
test/CodeGen/Thumb2/2009-07-21-ISelBug.ll
View File

@ -6,7 +6,7 @@
define arm_apcscc i32 @t(i32, ...) nounwind {
entry:
; CHECK: t:
; CHECK: add r7, sp, #3 * 4
; CHECK: add r7, sp, #12
%1 = load i8** undef, align 4 ; <i8*> [#uses=3]
%2 = getelementptr i8* %1, i32 4 ; <i8*> [#uses=1]
%3 = getelementptr i8* %1, i32 8 ; <i8*> [#uses=1]

2
test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll
View File

@ -6,7 +6,7 @@ define hidden arm_aapcscc i32 @__gcov_execlp(i8* %path, i8* %arg, ...) nounwind
entry:
; CHECK: __gcov_execlp:
; CHECK: mov sp, r7
; CHECK: sub sp, #1 * 4
; CHECK: sub sp, #4
call arm_aapcscc void @__gcov_flush() nounwind
br i1 undef, label %bb5, label %bb

6
test/CodeGen/Thumb2/large-stack.ll
View File

@ -2,7 +2,7 @@
define void @test1() {
; CHECK: test1:
; CHECK: sub sp, #64 * 4
; CHECK: sub sp, #256
%tmp = alloca [ 64 x i32 ] , align 4
ret void
}
@ -10,7 +10,7 @@ define void @test1() {
define void @test2() {
; CHECK: test2:
; CHECK: sub.w sp, sp, #4160
; CHECK: sub sp, #2 * 4
; CHECK: sub sp, #8
%tmp = alloca [ 4168 x i8 ] , align 4
ret void
}
@ -18,7 +18,7 @@ define void @test2() {
define i32 @test3() {
; CHECK: test3:
; CHECK: sub.w sp, sp, #805306368
; CHECK: sub sp, #6 * 4
; CHECK: sub sp, #24
%retval = alloca i32, align 4
%tmp = alloca i32, align 4
%a = alloca [805306369 x i8], align 16