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[ARM] Transform LDMs into writeback form to save code size

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If we have an LDM that uses only low registers and doesn't write to its base register:

  ldm.w r0, {r1, r2, r3}

And that base register is dead after the LDM, then we can convert it to writeback form and use a narrow encoding:

  ldm.n r0!, {r1, r2, r3}

Obviously, this introduces a new register write and so can cause WAW hazards, so I've enabled it only in minsize mode. This is a code size trick that ARM Compiler 5 ("armcc") does that we don't.

llvm-svn: 272000
This commit is contained in:
James Molloy 2016-06-07 11:47:24 +00:00
parent 37a7f50a87
commit 98866e3fe1
2 changed files with 44 additions and 3 deletions
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22
lib/Target/ARM/ARMLoadStoreOptimizer.cpp
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@ -1229,9 +1229,29 @@ bool ARMLoadStoreOpt::MergeBaseUpdateLSMultiple(MachineInstr *MI) {
} else { } else {
MergeInstr = findIncDecAfter(MBBI, Base, Pred, PredReg, Offset); MergeInstr = findIncDecAfter(MBBI, Base, Pred, PredReg, Offset);
if (((Mode != ARM_AM::ia && Mode != ARM_AM::ib) || Offset != Bytes) && if (((Mode != ARM_AM::ia && Mode != ARM_AM::ib) || Offset != Bytes) &&
((Mode != ARM_AM::da && Mode != ARM_AM::db) || Offset != -Bytes)) ((Mode != ARM_AM::da && Mode != ARM_AM::db) || Offset != -Bytes)) {
// We couldn't find an inc/dec to merge. But if the base is dead, we
// can still change to a writeback form as that will save us 2 bytes
// of code size. It can create WAW hazards though, so only do it if
// we're minimizing code size.
if (!MBB.getParent()->getFunction()->optForMinSize() || !BaseKill)
return false;
bool HighRegsUsed = false;
for (unsigned i = 2, e = MI->getNumOperands(); i != e; ++i)
if (MI->getOperand(i).getReg() >= ARM::R8) {
HighRegsUsed = true;
break;
}
if (!HighRegsUsed)
MergeInstr = MBB.end();
else
return false; return false;
} }
}
if (MergeInstr != MBB.end())
MBB.erase(MergeInstr); MBB.erase(MergeInstr);
unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode, Mode); unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode, Mode);

21
test/CodeGen/ARM/ldm-base-writeback.ll Normal file
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@ -0,0 +1,21 @@
; RUN: llc -O3 < %s | FileCheck %s
target datalayout = "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
target triple = "armv7--linux-gnu"
@a = global i32 0, align 4
@b = global i32 0, align 4
@c = global i32 0, align 4
; CHECK-LABEL: bar:
; CHECK: ldm r{{[0-9]}}!, {r0, r{{[0-9]}}, r{{[0-9]}}}
define void @bar(i32 %a1, i32 %b1, i32 %c1) minsize optsize {
%1 = load i32, i32* @a, align 4
%2 = load i32, i32* @b, align 4
%3 = load i32, i32* @c, align 4
%4 = tail call i32 @baz(i32 %1, i32 %3) minsize optsize
%5 = tail call i32 @baz(i32 %2, i32 %3) minsize optsize
ret void
}
declare i32 @baz(i32,i32) minsize optsize