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[ARM] Ensure we update the correct flags in the peephole optimiser
The Arm peephole optimiser code keeps track of both an MI and a SubAdd that can be used to optimise away a CMP. In the rare case that both are found and not ruled-out as valid, we could end up setting the flags on the wrong one. Instead make sure we are using SubAdd if it exists, as it will be closer to the CMP. The testcase here is a little theoretical, with a dead def of cpsr. It should hopefully show the point. Differential Revision: https://reviews.llvm.org/D58176 llvm-svn: 354018
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@ -2825,8 +2825,11 @@ bool ARMBaseInstrInfo::optimizeCompareInstr(
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if (!MI && !SubAdd)
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return false;
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// The single candidate is called MI.
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if (!MI) MI = SubAdd;
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// If we found a SubAdd, use it as it will be closer to the CMP
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if (SubAdd) {
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MI = SubAdd;
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IsThumb1 = false;
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}
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// We can't use a predicated instruction - it doesn't always write the flags.
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if (isPredicated(*MI))
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35
test/CodeGen/Thumb2/peephole-addsub.mir
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35
test/CodeGen/Thumb2/peephole-addsub.mir
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@ -0,0 +1,35 @@
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# RUN: llc -run-pass=peephole-opt -verify-machineinstrs -o - %s | FileCheck %s
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--- |
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target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv7-none-eabi"
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define i32 @test(i32 %a, i32 %b) {
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unreachable
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}
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...
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---
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name: test
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tracksRegLiveness: true
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liveins:
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- { reg: '$r0', virtual-reg: '%0' }
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- { reg: '$r1', virtual-reg: '%1' }
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body: |
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bb.0 (%ir-block.0):
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liveins: $r0, $r1
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%1:rgpr = COPY $r1
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%0:rgpr = COPY $r0
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%2:rgpr = t2MOVi 1, 14, $noreg, $noreg
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%3:gprnopc = t2ADDrr %0, %1, 14, $noreg, $noreg
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%4:gprnopc = t2SUBri %3, 0, 14, $noreg, def dead $cpsr
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t2CMPri killed %3, 0, 14, $noreg, implicit-def $cpsr
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%5:rgpr = t2MOVCCi %2, 0, 7, $cpsr
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$r0 = COPY %5
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tBX_RET 14, $noreg, implicit $r0
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# CHECK-LABEL: name: test
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# CHECK: %3:gprnopc = t2ADDrr %0, %1, 14, $noreg, $noreg
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# CHECK-NEXT: %4:gprnopc = t2SUBri %3, 0, 14, $noreg, def $cpsr
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# CHECK-NEXT: %5:rgpr = t2MOVCCi %2, 0, 7, $cpsr
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...
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