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[Hexagon] Remove encoding bits from mapped instructions
- Map A2_zxtb to A2_andir.
- Map PS_call_nr J2_call.
- Map A2_tfr[t|f][new] to A2_padd[t|f][new].
Patch by Colin LeMahieu.
llvm-svn: 294320
This commit is contained in:
Krzysztof Parzyszek
parent
60b80f3e0e
commit
98fb395668
@ -2198,6 +2198,11 @@ int HexagonAsmParser::processInstruction(MCInst &Inst,
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if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr()))
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Inst.setOpcode(Hexagon::S2_storerinewgp);
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break;
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case Hexagon::A2_zxtb: {
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Inst.setOpcode(Hexagon::A2_andir);
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Inst.addOperand(MCOperand::createExpr(MCConstantExpr::create(255, Context)));
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break;
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}
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} // switch
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return Match_Success;
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@ -282,6 +282,36 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst,
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break;
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}
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case Hexagon::A2_tfrf: {
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Inst.setOpcode(Hexagon::A2_paddif);
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Inst.addOperand(MCOperand::createExpr(MCConstantExpr::create(0, OutContext)));
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break;
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}
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case Hexagon::A2_tfrt: {
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Inst.setOpcode(Hexagon::A2_paddit);
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Inst.addOperand(MCOperand::createExpr(MCConstantExpr::create(0, OutContext)));
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break;
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}
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case Hexagon::A2_tfrfnew: {
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Inst.setOpcode(Hexagon::A2_paddifnew);
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Inst.addOperand(MCOperand::createExpr(MCConstantExpr::create(0, OutContext)));
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break;
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}
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case Hexagon::A2_tfrtnew: {
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Inst.setOpcode(Hexagon::A2_padditnew);
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Inst.addOperand(MCOperand::createExpr(MCConstantExpr::create(0, OutContext)));
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break;
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}
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case Hexagon::A2_zxtb: {
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Inst.setOpcode(Hexagon::A2_andir);
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Inst.addOperand(MCOperand::createExpr(MCConstantExpr::create(255, OutContext)));
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break;
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}
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// "$dst = CONST64(#$src1)",
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case Hexagon::CONST64:
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if (!OutStreamer->hasRawTextSupport()) {
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@ -376,6 +406,9 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst,
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Rs.setReg(getHexagonRegisterPair(Rs.getReg(), RI));
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return;
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}
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case Hexagon::PS_call_nr:
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Inst.setOpcode(Hexagon::J2_call);
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break;
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case Hexagon::S5_asrhub_rnd_sat_goodsyntax: {
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MCOperand &MO = MappedInst.getOperand(2);
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int64_t Imm;
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@ -401,13 +401,12 @@ def A2_tfril: T_tfr16<0>;
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def A2_tfrih: T_tfr16<1>;
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// Conditional transfer is an alias to conditional "Rd = add(Rs, #0)".
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let isPredicated = 1, hasNewValue = 1, opNewValue = 0 in
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let isPredicated = 1, hasNewValue = 1, isCodeGenOnly = 1, opNewValue = 0,
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isPseudo = 1 in
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class T_tfr_pred<bit isPredNot, bit isPredNew>
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: ALU32Inst<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2),
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"if ("#!if(isPredNot, "!", "")#
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"$src1"#!if(isPredNew, ".new", "")#
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") $dst = $src2"> {
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""> {
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bits<5> dst;
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bits<2> src1;
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bits<5> src2;
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@ -487,6 +486,11 @@ multiclass TFR64_base<string BaseName> {
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}
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}
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def A2_tfrfAlias : InstAlias<"if (!$Pu4) $Rd32=$Rs32", (A2_paddif IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$Rs32, 0)>;
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def A2_tfrfnewAlias : InstAlias<"if (!$Pu4.new) $Rd32=$Rs32", (A2_paddifnew IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$Rs32, 0)>;
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def A2_tfrtAlias : InstAlias<"if ($Pu4) $Rd32=$Rs32", (A2_paddit IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$Rs32, 0)>;
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def A2_tfrtnewAlias : InstAlias<"if ($Pu4.new) $Rd32=$Rs32", (A2_padditnew IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$Rs32, 0)>;
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let InputType = "imm", isExtendable = 1, isExtentSigned = 1, opExtentBits = 12,
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isMoveImm = 1, opExtendable = 2, BaseOpcode = "TFRI", CextOpcode = "TFR",
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hasSideEffects = 0, isPredicated = 1, hasNewValue = 1 in
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@ -699,19 +703,7 @@ defm zxth : ALU32_2op_base<"zxth", 0b110>, PredNewRel;
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let hasNewValue = 1, opNewValue = 0 in
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class T_ZXTB: ALU32Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rs),
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"$Rd = zxtb($Rs)", [] > { // Rd = and(Rs,255)
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bits<5> Rd;
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bits<5> Rs;
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bits<10> s10 = 255;
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let IClass = 0b0111;
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let Inst{27-22} = 0b011000;
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let Inst{4-0} = Rd;
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let Inst{20-16} = Rs;
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let Inst{21} = s10{9};
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let Inst{13-5} = s10{8-0};
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}
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"$Rd=zxtb($Rs)", [] >;
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//Rd=zxtb(Rs): assembler mapped to "Rd=and(Rs,#255)
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multiclass ZXTB_base <string mnemonic, bits<3> minOp> {
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@ -61,7 +61,7 @@ multiclass T_Calls<bit CSR, string ExtStr> {
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defm J2_call: T_Calls<1, "">, PredRel;
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let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1,
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Defs = VolatileV3.Regs in
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Defs = VolatileV3.Regs, isPseudo = 1 in
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def PS_call_nr : T_Call<1, "">, PredRel;
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let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1,
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94
test/CodeGen/Hexagon/swp-stages4.ll
Normal file
94
test/CodeGen/Hexagon/swp-stages4.ll
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@ -0,0 +1,94 @@
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; RUN: llc -march=hexagon -mcpu=hexagonv5 -enable-pipeliner -pipeliner-max-stages=2 -disable-block-placement=0 -hexagon-bit=0 < %s | FileCheck %s
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; Test that we rename registers correctly for multiple stages when there is a
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; Phi and depends upon another Phi.
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; CHECK: = and
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; CHECK: = and
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; CHECK: = and
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; CHECK: [[REG0:(r[0-9]+)]] = and([[REG1:(r[0-9]+)]], #255)
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; CHECK-NOT: [[REG0]] = and([[REG1]], #255)
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; CHECK: loop0(.LBB0_[[LOOP:.]],
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; CHECK: .LBB0_[[LOOP]]:
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; CHECK: [[REG0]] += add
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; CHECK: = and
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; CHECK: = and
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; CHECK: [[REG0]] = and
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; CHECK: endloop
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; Function Attrs: nounwind
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define void @test(i8* noalias nocapture %src, i32 %srcWidth, i32 %srcHeight, i32 %srcStride, i8* noalias nocapture %dst, i32 %dstStride) #0 {
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entry:
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%sub = add i32 %srcWidth, -1
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%sub1 = add i32 %srcHeight, -1
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%add.ptr = getelementptr inbounds i8, i8* %src, i32 %srcStride
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%add.ptr.sum = mul i32 %srcStride, 2
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%add.ptr2 = getelementptr inbounds i8, i8* %src, i32 %add.ptr.sum
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br label %for.body.lr.ph
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for.body.lr.ph:
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%0 = add i32 %srcHeight, -2
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%1 = mul i32 %0, %dstStride
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%2 = mul i32 %0, %srcStride
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%3 = mul i32 %sub1, %srcStride
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br label %for.cond
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for.cond:
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%scevgep = getelementptr i8, i8* %dst, i32 %1
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%scevgep220 = getelementptr i8, i8* %src, i32 %2
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%scevgep221 = getelementptr i8, i8* %src, i32 %3
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%arrayidx6 = getelementptr inbounds i8, i8* %src, i32 1
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%add11 = add i32 %srcStride, 1
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%arrayidx12 = getelementptr inbounds i8, i8* %src, i32 %add11
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br label %for.body75.preheader
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for.body75.preheader:
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%sri = load i8, i8* %arrayidx6, align 1
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%sri224 = load i8, i8* %src, align 1
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%sri227 = load i8, i8* %arrayidx12, align 1
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%sri229 = load i8, i8* %add.ptr, align 1
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br label %for.body75
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for.body75:
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%j.0211 = phi i32 [ %add82, %for.body75 ], [ 1, %for.body75.preheader ]
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%sr = phi i8 [ %4, %for.body75 ], [ %sri, %for.body75.preheader ]
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%sr225 = phi i8 [ %sr, %for.body75 ], [ %sri224, %for.body75.preheader ]
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%sr230 = phi i8 [ %5, %for.body75 ], [ %sri227, %for.body75.preheader ]
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%sr231 = phi i8 [ %sr230, %for.body75 ], [ %sri229, %for.body75.preheader ]
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%conv78 = zext i8 %sr225 to i32
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%conv80 = zext i8 %sr to i32
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%add81 = add nsw i32 %conv80, %conv78
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%add82 = add i32 %j.0211, 1
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%arrayidx83 = getelementptr inbounds i8, i8* %src, i32 %add82
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%4 = load i8, i8* %arrayidx83, align 1, !tbaa !0
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%conv84 = zext i8 %4 to i32
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%add85 = add nsw i32 %add81, %conv84
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%conv88 = zext i8 %sr231 to i32
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%add89 = add nsw i32 %add85, %conv88
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%conv91 = zext i8 %sr230 to i32
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%add92 = add nsw i32 %add89, %conv91
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%add.ptr.sum208 = add i32 %add82, %srcStride
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%arrayidx94 = getelementptr inbounds i8, i8* %src, i32 %add.ptr.sum208
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%5 = load i8, i8* %arrayidx94, align 1, !tbaa !0
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%conv95 = zext i8 %5 to i32
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%add96 = add nsw i32 %add92, %conv95
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%mul97 = mul nsw i32 %add96, 7282
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%add98 = add nsw i32 %mul97, 32768
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%shr99209 = lshr i32 %add98, 16
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%conv100 = trunc i32 %shr99209 to i8
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%arrayidx101 = getelementptr inbounds i8, i8* %dst, i32 %j.0211
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store i8 %conv100, i8* %arrayidx101, align 1, !tbaa !0
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%exitcond = icmp eq i32 %add82, %sub
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br i1 %exitcond, label %for.end104.loopexit, label %for.body75
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for.end104.loopexit:
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br label %for.end104
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for.end104:
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ret void
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}
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attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
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!0 = !{!"omnipotent char", !1}
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!1 = !{!"Simple C/C++ TBAA"}
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78
test/CodeGen/Hexagon/swp-stages5.ll
Normal file
78
test/CodeGen/Hexagon/swp-stages5.ll
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@ -0,0 +1,78 @@
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; RUN: llc -march=hexagon -mcpu=hexagonv5 -enable-pipeliner -pipeliner-max-stages=2 -hexagon-bit=0 < %s | FileCheck %s
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; Very similar to swp-stages4.ll, but the pipelined schedule is a little
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; different.
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; CHECK: = memub(r{{[0-9]+}}++#1)
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; CHECK-DAG: [[REG0:(r[0-9]+)]] = memub(r{{[0-9]+}}++#1)
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; CHECK-DAG: loop0(.LBB0_[[LOOP:.]],
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; CHECK: .LBB0_[[LOOP]]:
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; CHECK: = and([[REG0]], #255)
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; CHECK: [[REG0]]{{[:0-9]*}} =
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; CHECK: endloop
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define void @fred(i8* noalias nocapture %src, i32 %srcWidth, i32 %srcHeight, i32 %srcStride, i8* noalias nocapture %dst, i32 %dstStride) #0 {
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entry:
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%sub = add i32 %srcWidth, -1
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%sub1 = add i32 %srcHeight, -1
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%add.ptr = getelementptr inbounds i8, i8* %src, i32 %srcStride
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%add.ptr.sum = mul i32 %srcStride, 2
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%add.ptr2 = getelementptr inbounds i8, i8* %src, i32 %add.ptr.sum
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%cmp212 = icmp ugt i32 %sub1, 1
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br i1 %cmp212, label %for.body.lr.ph, label %for.end
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for.body.lr.ph:
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br label %for.body74.preheader
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for.body74.preheader:
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%0 = load i8, i8* %add.ptr, align 1, !tbaa !0
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%arrayidx40 = getelementptr inbounds i8, i8* %add.ptr, i32 1
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%1 = load i8, i8* %arrayidx40, align 1, !tbaa !0
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%2 = load i8, i8* %add.ptr, align 1, !tbaa !0
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%arrayidx46 = getelementptr inbounds i8, i8* %add.ptr, i32 1
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%3 = load i8, i8* %arrayidx46, align 1, !tbaa !0
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br label %for.body74
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for.body74:
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%4 = phi i8 [ %9, %for.body74 ], [ %3, %for.body74.preheader ]
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%5 = phi i8 [ %4, %for.body74 ], [ %2, %for.body74.preheader ]
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%6 = phi i8 [ %8, %for.body74 ], [ %1, %for.body74.preheader ]
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%7 = phi i8 [ %6, %for.body74 ], [ %0, %for.body74.preheader ]
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%j.0211 = phi i32 [ %add81, %for.body74 ], [ 1, %for.body74.preheader ]
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%conv77 = zext i8 %7 to i32
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%conv79 = zext i8 %6 to i32
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%add80 = add nsw i32 %conv79, %conv77
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%add81 = add i32 %j.0211, 1
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%arrayidx82 = getelementptr inbounds i8, i8* %src, i32 %add81
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%8 = load i8, i8* %arrayidx82, align 1, !tbaa !0
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%conv83 = zext i8 %8 to i32
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%add84 = add nsw i32 %add80, %conv83
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%conv87 = zext i8 %5 to i32
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%add88 = add nsw i32 %add84, %conv87
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%conv90 = zext i8 %4 to i32
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%add91 = add nsw i32 %add88, %conv90
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%arrayidx93 = getelementptr inbounds i8, i8* %add.ptr, i32 %add81
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%9 = load i8, i8* %arrayidx93, align 1, !tbaa !0
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%conv94 = zext i8 %9 to i32
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%add95 = add nsw i32 %add91, %conv94
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%mul96 = mul nsw i32 %add95, 7282
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%add97 = add nsw i32 %mul96, 32768
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%shr98208 = lshr i32 %add97, 16
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%conv99 = trunc i32 %shr98208 to i8
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%add.ptr5.sum209 = add i32 %j.0211, %dstStride
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%arrayidx100 = getelementptr inbounds i8, i8* %dst, i32 %add.ptr5.sum209
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store i8 %conv99, i8* %arrayidx100, align 1, !tbaa !0
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%exitcond = icmp eq i32 %add81, %sub
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br i1 %exitcond, label %for.end103.loopexit, label %for.body74
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for.end103.loopexit:
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br label %for.end
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for.end:
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ret void
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}
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attributes #0 = { nounwind }
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!0 = !{!"omnipotent char", !1}
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!1 = !{!"Simple C/C++ TBAA"}
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@ -540,10 +540,10 @@ r5=zxtb(r20)
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p0=cmp.eq(r0,##179976360)
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}
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#CHECK: 74f9c00f { if (!p3) r15{{ *}}={{ *}}r25
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#CHECK: 74f9c00f { if (!p3) r15{{ *}} ={{ *}}add(r25, #0)
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if (!p3) r15=r25
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#CHECK: 7425c005 { if (p1) r5{{ *}}={{ *}}r5
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#CHECK: 7425c005 { if (p1) r5{{ *}}={{ *}}add(r5, #0)
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if (p1) r5=r5
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#CHECK: e9badae2 { r2{{ *}}={{ *}}vrcmpys(r27:26, r27:26):<<1:rnd:sat:raw:lo
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@ -561,7 +561,7 @@ if (!p2) r3:2=r7:6
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#CHECK: fd0dcc7e { if (p3) r31:30{{ *}}={{ *}}{{r13:12|combine\(r13, *r12\)}}
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if (p3) r31:30=r13:12
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#CHECK: 748ae015 if (!p0.new) r21{{ *}}={{ *}}r10
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#CHECK: 748ae015 if (!p0.new) r21{{ *}}={{ *}}add(r10, #0)
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{
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p0=cmp.eq(r23,##805633208)
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if (!p0.new) r21=r10
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@ -605,4 +605,4 @@ r19:18=vrcmpys(r11:10,r16):<<1:sat
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r21:20=memb_fifo(r2)
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#CHECK: 9056c01c { r29:28{{ *}}={{ *}}memh_fifo(r22{{ *}}+{{ *}}#0)
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r29:28=memh_fifo(r22)
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r29:28=memh_fifo(r22)
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