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[X86] Fix variadic argument handling for x32
The X86-64 ABI defines va_list as
typedef struct {
unsigned int gp_offset;
unsigned int fp_offset;
void *overflow_arg_area;
void *reg_save_area;
} va_list[1];
This means the size, alignment, and reg_save_area offset will depend on
whether we are in LP64 or in ILP32 mode, so this commit adds the checks.
Additionally, the VAARG_64 pseudo-instruction assumed 64-bit pointers, so
this commit adds a VAARG_X32 pseudo-instruction that behaves just like
VAARG_64, except for assuming 32-bit pointers.
Some of these changes were originally done by
Michael Liao <michael.hliao@gmail.com>.
Fixes https://bugs.llvm.org/show_bug.cgi?id=48428.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D93160
This commit is contained in:
Harald van Dijk
parent
05dd4fb241
commit
9906752fd3
@ -24360,15 +24360,16 @@ SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
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Subtarget.hasSSE1());
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}
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// Insert VAARG_64 node into the DAG
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// VAARG_64 returns two values: Variable Argument Address, Chain
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// Insert VAARG node into the DAG
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// VAARG returns two values: Variable Argument Address, Chain
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SDValue InstOps[] = {Chain, SrcPtr,
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DAG.getTargetConstant(ArgSize, dl, MVT::i32),
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DAG.getTargetConstant(ArgMode, dl, MVT::i8),
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DAG.getTargetConstant(Align, dl, MVT::i32)};
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SDVTList VTs = DAG.getVTList(getPointerTy(DAG.getDataLayout()), MVT::Other);
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SDValue VAARG = DAG.getMemIntrinsicNode(
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X86ISD::VAARG_64, dl, VTs, InstOps, MVT::i64, MachinePointerInfo(SV),
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Subtarget.isTarget64BitLP64() ? X86ISD::VAARG_64 : X86ISD::VAARG_X32, dl,
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VTs, InstOps, MVT::i64, MachinePointerInfo(SV),
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/*Alignment=*/None,
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MachineMemOperand::MOLoad | MachineMemOperand::MOStore);
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Chain = VAARG.getValue(1);
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@ -24394,9 +24395,11 @@ static SDValue LowerVACOPY(SDValue Op, const X86Subtarget &Subtarget,
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const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
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SDLoc DL(Op);
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return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, DAG.getIntPtrConstant(24, DL),
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Align(8), /*isVolatile*/ false, false, false,
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MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
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return DAG.getMemcpy(
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Chain, DL, DstPtr, SrcPtr,
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DAG.getIntPtrConstant(Subtarget.isTarget64BitLP64() ? 24 : 16, DL),
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Align(Subtarget.isTarget64BitLP64() ? 8 : 4), /*isVolatile*/ false, false,
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false, MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
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}
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// Helper to get immediate/variable SSE shift opcode from other shift opcodes.
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@ -30959,6 +30962,7 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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NODE_NAME_CASE(DBPSADBW)
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NODE_NAME_CASE(VASTART_SAVE_XMM_REGS)
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NODE_NAME_CASE(VAARG_64)
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NODE_NAME_CASE(VAARG_X32)
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NODE_NAME_CASE(WIN_ALLOCA)
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NODE_NAME_CASE(MEMBARRIER)
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NODE_NAME_CASE(MFENCE)
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@ -31548,11 +31552,9 @@ static MachineBasicBlock *emitXBegin(MachineInstr &MI, MachineBasicBlock *MBB,
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return sinkMBB;
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}
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MachineBasicBlock *
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X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr &MI,
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MachineBasicBlock *MBB) const {
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X86TargetLowering::EmitVAARGWithCustomInserter(MachineInstr &MI,
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MachineBasicBlock *MBB) const {
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// Emit va_arg instruction on X86-64.
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// Operands to this pseudo-instruction:
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@ -31563,9 +31565,8 @@ X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr &MI,
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// 8 ) Align : Alignment of type
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// 9 ) EFLAGS (implicit-def)
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assert(MI.getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
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static_assert(X86::AddrNumOperands == 5,
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"VAARG_64 assumes 5 address operands");
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assert(MI.getNumOperands() == 10 && "VAARG should have 10 operands!");
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static_assert(X86::AddrNumOperands == 5, "VAARG assumes 5 address operands");
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Register DestReg = MI.getOperand(0).getReg();
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MachineOperand &Base = MI.getOperand(1);
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@ -31580,7 +31581,7 @@ X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr &MI,
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MachineFunction *MF = MBB->getParent();
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// Memory Reference
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assert(MI.hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
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assert(MI.hasOneMemOperand() && "Expected VAARG to have one memoperand");
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MachineMemOperand *OldMMO = MI.memoperands().front();
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@ -31593,7 +31594,8 @@ X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr &MI,
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// Machine Information
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const TargetInstrInfo *TII = Subtarget.getInstrInfo();
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MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
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const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
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const TargetRegisterClass *AddrRegClass =
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getRegClassFor(getPointerTy(MBB->getParent()->getDataLayout()));
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const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
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const DebugLoc &DL = MI.getDebugLoc();
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@ -31704,25 +31706,35 @@ X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr &MI,
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// Read the reg_save_area address.
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Register RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
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BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
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BuildMI(
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offsetMBB, DL,
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TII->get(Subtarget.isTarget64BitLP64() ? X86::MOV64rm : X86::MOV32rm),
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RegSaveReg)
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.add(Base)
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.add(Scale)
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.add(Index)
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.addDisp(Disp, 16)
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.addDisp(Disp, Subtarget.isTarget64BitLP64() ? 16 : 12)
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.add(Segment)
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.setMemRefs(LoadOnlyMMO);
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// Zero-extend the offset
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Register OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
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BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
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.addImm(0)
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.addReg(OffsetReg)
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.addImm(X86::sub_32bit);
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if (Subtarget.isTarget64BitLP64()) {
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// Zero-extend the offset
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Register OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
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BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
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.addImm(0)
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.addReg(OffsetReg)
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.addImm(X86::sub_32bit);
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// Add the offset to the reg_save_area to get the final address.
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BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
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.addReg(OffsetReg64)
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.addReg(RegSaveReg);
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// Add the offset to the reg_save_area to get the final address.
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BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
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.addReg(OffsetReg64)
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.addReg(RegSaveReg);
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} else {
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// Add the offset to the reg_save_area to get the final address.
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BuildMI(offsetMBB, DL, TII->get(X86::ADD32rr), OffsetDestReg)
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.addReg(OffsetReg)
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.addReg(RegSaveReg);
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}
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// Compute the offset for the next argument
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Register NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
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@ -31751,7 +31763,9 @@ X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr &MI,
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// Load the overflow_area address into a register.
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Register OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
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BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
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BuildMI(overflowMBB, DL,
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TII->get(Subtarget.isTarget64BitLP64() ? X86::MOV64rm : X86::MOV32rm),
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OverflowAddrReg)
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.add(Base)
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.add(Scale)
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.add(Index)
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@ -31766,11 +31780,17 @@ X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr &MI,
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Register TmpReg = MRI.createVirtualRegister(AddrRegClass);
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// aligned_addr = (addr + (align-1)) & ~(align-1)
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BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
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BuildMI(
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overflowMBB, DL,
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TII->get(Subtarget.isTarget64BitLP64() ? X86::ADD64ri32 : X86::ADD32ri),
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TmpReg)
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.addReg(OverflowAddrReg)
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.addImm(Alignment.value() - 1);
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BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
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BuildMI(
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overflowMBB, DL,
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TII->get(Subtarget.isTarget64BitLP64() ? X86::AND64ri32 : X86::AND32ri),
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OverflowDestReg)
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.addReg(TmpReg)
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.addImm(~(uint64_t)(Alignment.value() - 1));
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} else {
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@ -31781,12 +31801,16 @@ X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr &MI,
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// Compute the next overflow address after this argument.
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// (the overflow address should be kept 8-byte aligned)
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Register NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
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BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
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.addReg(OverflowDestReg)
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.addImm(ArgSizeA8);
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BuildMI(
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overflowMBB, DL,
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TII->get(Subtarget.isTarget64BitLP64() ? X86::ADD64ri32 : X86::ADD32ri),
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NextAddrReg)
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.addReg(OverflowDestReg)
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.addImm(ArgSizeA8);
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// Store the new overflow address.
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BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
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BuildMI(overflowMBB, DL,
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TII->get(Subtarget.isTarget64BitLP64() ? X86::MOV64mr : X86::MOV32mr))
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.add(Base)
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.add(Scale)
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.add(Index)
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@ -33721,7 +33745,8 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
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return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
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case X86::VAARG_64:
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return EmitVAARG64WithCustomInserter(MI, BB);
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case X86::VAARG_X32:
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return EmitVAARGWithCustomInserter(MI, BB);
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case X86::EH_SjLj_SetJmp32:
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case X86::EH_SjLj_SetJmp64:
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@ -814,9 +814,10 @@ namespace llvm {
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/// specifies the type to store as.
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FST,
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/// This instruction grabs the address of the next argument
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/// These instructions grab the address of the next argument
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/// from a va_list. (reads and modifies the va_list in memory)
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VAARG_64,
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VAARG_X32,
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// Vector truncating store with unsigned/signed saturation
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VTRUNCSTOREUS,
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@ -1581,8 +1582,7 @@ namespace llvm {
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// Utility function to emit the low-level va_arg code for X86-64.
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MachineBasicBlock *
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EmitVAARG64WithCustomInserter(MachineInstr &MI,
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MachineBasicBlock *MBB) const;
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EmitVAARGWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const;
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/// Utility function to emit the xmm reg save portion of va_start.
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MachineBasicBlock *
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@ -81,17 +81,24 @@ def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
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timm:$offset),
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(implicit EFLAGS)]>;
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// The VAARG_64 pseudo-instruction takes the address of the va_list,
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// and places the address of the next argument into a register.
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let Defs = [EFLAGS] in
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// The VAARG_64 and VAARG_X32 pseudo-instructions take the address of the
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// va_list, and place the address of the next argument into a register.
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let Defs = [EFLAGS] in {
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def VAARG_64 : I<0, Pseudo,
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(outs GR64:$dst),
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(ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align),
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"#VAARG_64 $dst, $ap, $size, $mode, $align",
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[(set GR64:$dst,
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(X86vaarg64 addr:$ap, timm:$size, timm:$mode, timm:$align)),
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(implicit EFLAGS)]>;
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(implicit EFLAGS)]>, Requires<[In64BitMode, IsLP64]>;
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def VAARG_X32 : I<0, Pseudo,
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(outs GR32:$dst),
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(ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align),
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"#VAARG_X32 $dst, $ap, $size, $mode, $align",
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[(set GR32:$dst,
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(X86vaargx32 addr:$ap, timm:$size, timm:$mode, timm:$align)),
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(implicit EFLAGS)]>, Requires<[In64BitMode, NotLP64]>;
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}
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// When using segmented stacks these are lowered into instructions which first
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// check if the current stacklet has enough free memory. If it does, memory is
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@ -94,11 +94,11 @@ def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
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SDTCisVT<1, iPTR>,
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SDTCisVT<2, iPTR>]>;
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def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>,
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SDTCisPtrTy<1>,
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SDTCisVT<2, i32>,
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SDTCisVT<3, i8>,
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SDTCisVT<4, i32>]>;
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def SDT_X86VAARG : SDTypeProfile<1, -1, [SDTCisPtrTy<0>,
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SDTCisPtrTy<1>,
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SDTCisVT<2, i32>,
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SDTCisVT<3, i8>,
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SDTCisVT<4, i32>]>;
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def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
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@ -186,7 +186,11 @@ def X86vastart_save_xmm_regs :
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SDT_X86VASTART_SAVE_XMM_REGS,
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[SDNPHasChain, SDNPVariadic]>;
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def X86vaarg64 :
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SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64,
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SDNode<"X86ISD::VAARG_64", SDT_X86VAARG,
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[SDNPHasChain, SDNPMayLoad, SDNPMayStore,
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SDNPMemOperand]>;
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def X86vaargx32 :
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SDNode<"X86ISD::VAARG_X32", SDT_X86VAARG,
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[SDNPHasChain, SDNPMayLoad, SDNPMayStore,
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SDNPMemOperand]>;
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def X86callseq_start :
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@ -1,5 +1,6 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --no_x86_scrub_sp
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -code-model=large -relocation-model=static | FileCheck --check-prefix=CHECK-X64 %s
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; RUN: llc < %s -mtriple=x86_64-linux-gnux32 | FileCheck --check-prefix=CHECK-X32 %s
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@.str = internal constant [38 x i8] c"%d, %f, %d, %lld, %d, %f, %d, %d, %d\0A\00" ; <[38 x i8]*> [#uses=1]
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@ -271,6 +272,261 @@ define void @func(...) nounwind {
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; CHECK-X64-NEXT: addq $240, %rsp
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; CHECK-X64-NEXT: popq %rbx
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; CHECK-X64-NEXT: retq
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;
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; CHECK-X32-LABEL: func:
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; CHECK-X32: # %bb.0: # %entry
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; CHECK-X32-NEXT: subl $216, %esp
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; CHECK-X32-NEXT: testb %al, %al
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; CHECK-X32-NEXT: je .LBB0_2
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; CHECK-X32-NEXT: # %bb.1: # %entry
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; CHECK-X32-NEXT: movaps %xmm0, 80(%esp)
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; CHECK-X32-NEXT: movaps %xmm1, 96(%esp)
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; CHECK-X32-NEXT: movaps %xmm2, 112(%esp)
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; CHECK-X32-NEXT: movaps %xmm3, 128(%esp)
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; CHECK-X32-NEXT: movaps %xmm4, 144(%esp)
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; CHECK-X32-NEXT: movaps %xmm5, 160(%esp)
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; CHECK-X32-NEXT: movaps %xmm6, 176(%esp)
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; CHECK-X32-NEXT: movaps %xmm7, 192(%esp)
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; CHECK-X32-NEXT: .LBB0_2: # %entry
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; CHECK-X32-NEXT: movq %rdi, 32(%esp)
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; CHECK-X32-NEXT: movq %rsi, 40(%esp)
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; CHECK-X32-NEXT: movq %rdx, 48(%esp)
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; CHECK-X32-NEXT: movq %rcx, 56(%esp)
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; CHECK-X32-NEXT: movq %r8, 64(%esp)
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; CHECK-X32-NEXT: movq %r9, 72(%esp)
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; CHECK-X32-NEXT: movabsq $206158430208, %rax # imm = 0x3000000000
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; CHECK-X32-NEXT: movq %rax, (%esp)
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; CHECK-X32-NEXT: leal 224(%rsp), %eax
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; CHECK-X32-NEXT: movl %eax, 8(%esp)
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; CHECK-X32-NEXT: leal 32(%rsp), %eax
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; CHECK-X32-NEXT: movl %eax, 12(%esp)
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; CHECK-X32-NEXT: movl (%esp), %ecx
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; CHECK-X32-NEXT: cmpl $48, %ecx
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; CHECK-X32-NEXT: jae .LBB0_4
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; CHECK-X32-NEXT: # %bb.3: # %entry
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; CHECK-X32-NEXT: movl 12(%esp), %eax
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; CHECK-X32-NEXT: addl %ecx, %eax
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; CHECK-X32-NEXT: addl $8, %ecx
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; CHECK-X32-NEXT: movl %ecx, (%esp)
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; CHECK-X32-NEXT: jmp .LBB0_5
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; CHECK-X32-NEXT: .LBB0_4: # %entry
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; CHECK-X32-NEXT: movl 8(%esp), %eax
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; CHECK-X32-NEXT: movl %eax, %ecx
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; CHECK-X32-NEXT: addl $8, %ecx
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; CHECK-X32-NEXT: movl %ecx, 8(%esp)
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; CHECK-X32-NEXT: .LBB0_5: # %entry
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; CHECK-X32-NEXT: movl (%eax), %r10d
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; CHECK-X32-NEXT: movl (%esp), %ecx
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; CHECK-X32-NEXT: cmpl $48, %ecx
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; CHECK-X32-NEXT: jae .LBB0_7
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; CHECK-X32-NEXT: # %bb.6: # %entry
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; CHECK-X32-NEXT: movl 12(%esp), %eax
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; CHECK-X32-NEXT: addl %ecx, %eax
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; CHECK-X32-NEXT: addl $8, %ecx
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; CHECK-X32-NEXT: movl %ecx, (%esp)
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; CHECK-X32-NEXT: jmp .LBB0_8
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; CHECK-X32-NEXT: .LBB0_7: # %entry
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; CHECK-X32-NEXT: movl 8(%esp), %eax
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||||
; CHECK-X32-NEXT: movl %eax, %ecx
|
||||
; CHECK-X32-NEXT: addl $8, %ecx
|
||||
; CHECK-X32-NEXT: movl %ecx, 8(%esp)
|
||||
; CHECK-X32-NEXT: .LBB0_8: # %entry
|
||||
; CHECK-X32-NEXT: movl (%eax), %r11d
|
||||
; CHECK-X32-NEXT: movl (%esp), %ecx
|
||||
; CHECK-X32-NEXT: cmpl $48, %ecx
|
||||
; CHECK-X32-NEXT: jae .LBB0_10
|
||||
; CHECK-X32-NEXT: # %bb.9: # %entry
|
||||
; CHECK-X32-NEXT: movl 12(%esp), %eax
|
||||
; CHECK-X32-NEXT: addl %ecx, %eax
|
||||
; CHECK-X32-NEXT: addl $8, %ecx
|
||||
; CHECK-X32-NEXT: movl %ecx, (%esp)
|
||||
; CHECK-X32-NEXT: jmp .LBB0_11
|
||||
; CHECK-X32-NEXT: .LBB0_10: # %entry
|
||||
; CHECK-X32-NEXT: movl 8(%esp), %eax
|
||||
; CHECK-X32-NEXT: movl %eax, %ecx
|
||||
; CHECK-X32-NEXT: addl $8, %ecx
|
||||
; CHECK-X32-NEXT: movl %ecx, 8(%esp)
|
||||
; CHECK-X32-NEXT: .LBB0_11: # %entry
|
||||
; CHECK-X32-NEXT: movl (%eax), %r9d
|
||||
; CHECK-X32-NEXT: movq (%esp), %rax
|
||||
; CHECK-X32-NEXT: movq 8(%esp), %rcx
|
||||
; CHECK-X32-NEXT: movq %rcx, 24(%esp)
|
||||
; CHECK-X32-NEXT: movq %rax, 16(%esp)
|
||||
; CHECK-X32-NEXT: movl 4(%esp), %eax
|
||||
; CHECK-X32-NEXT: cmpl $176, %eax
|
||||
; CHECK-X32-NEXT: jae .LBB0_13
|
||||
; CHECK-X32-NEXT: # %bb.12: # %entry
|
||||
; CHECK-X32-NEXT: addl $16, %eax
|
||||
; CHECK-X32-NEXT: movl %eax, 4(%esp)
|
||||
; CHECK-X32-NEXT: jmp .LBB0_14
|
||||
; CHECK-X32-NEXT: .LBB0_13: # %entry
|
||||
; CHECK-X32-NEXT: movl 8(%esp), %eax
|
||||
; CHECK-X32-NEXT: addl $8, %eax
|
||||
; CHECK-X32-NEXT: movl %eax, 8(%esp)
|
||||
; CHECK-X32-NEXT: .LBB0_14: # %entry
|
||||
; CHECK-X32-NEXT: movl 20(%esp), %ecx
|
||||
; CHECK-X32-NEXT: cmpl $176, %ecx
|
||||
; CHECK-X32-NEXT: jae .LBB0_16
|
||||
; CHECK-X32-NEXT: # %bb.15: # %entry
|
||||
; CHECK-X32-NEXT: movl 28(%esp), %eax
|
||||
; CHECK-X32-NEXT: addl %ecx, %eax
|
||||
; CHECK-X32-NEXT: addl $16, %ecx
|
||||
; CHECK-X32-NEXT: movl %ecx, 20(%esp)
|
||||
; CHECK-X32-NEXT: jmp .LBB0_17
|
||||
; CHECK-X32-NEXT: .LBB0_16: # %entry
|
||||
; CHECK-X32-NEXT: movl 24(%esp), %eax
|
||||
; CHECK-X32-NEXT: movl %eax, %ecx
|
||||
; CHECK-X32-NEXT: addl $8, %ecx
|
||||
; CHECK-X32-NEXT: movl %ecx, 24(%esp)
|
||||
; CHECK-X32-NEXT: .LBB0_17: # %entry
|
||||
; CHECK-X32-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
|
||||
; CHECK-X32-NEXT: movl (%esp), %ecx
|
||||
; CHECK-X32-NEXT: cmpl $48, %ecx
|
||||
; CHECK-X32-NEXT: jae .LBB0_19
|
||||
; CHECK-X32-NEXT: # %bb.18: # %entry
|
||||
; CHECK-X32-NEXT: movl 12(%esp), %eax
|
||||
; CHECK-X32-NEXT: addl %ecx, %eax
|
||||
; CHECK-X32-NEXT: addl $8, %ecx
|
||||
; CHECK-X32-NEXT: movl %ecx, (%esp)
|
||||
; CHECK-X32-NEXT: jmp .LBB0_20
|
||||
; CHECK-X32-NEXT: .LBB0_19: # %entry
|
||||
; CHECK-X32-NEXT: movl 8(%esp), %eax
|
||||
; CHECK-X32-NEXT: movl %eax, %ecx
|
||||
; CHECK-X32-NEXT: addl $8, %ecx
|
||||
; CHECK-X32-NEXT: movl %ecx, 8(%esp)
|
||||
; CHECK-X32-NEXT: .LBB0_20: # %entry
|
||||
; CHECK-X32-NEXT: movl (%eax), %r8d
|
||||
; CHECK-X32-NEXT: movl 16(%esp), %eax
|
||||
; CHECK-X32-NEXT: cmpl $48, %eax
|
||||
; CHECK-X32-NEXT: jae .LBB0_22
|
||||
; CHECK-X32-NEXT: # %bb.21: # %entry
|
||||
; CHECK-X32-NEXT: addl $8, %eax
|
||||
; CHECK-X32-NEXT: movl %eax, 16(%esp)
|
||||
; CHECK-X32-NEXT: jmp .LBB0_23
|
||||
; CHECK-X32-NEXT: .LBB0_22: # %entry
|
||||
; CHECK-X32-NEXT: movl 24(%esp), %eax
|
||||
; CHECK-X32-NEXT: addl $8, %eax
|
||||
; CHECK-X32-NEXT: movl %eax, 24(%esp)
|
||||
; CHECK-X32-NEXT: .LBB0_23: # %entry
|
||||
; CHECK-X32-NEXT: movl (%esp), %eax
|
||||
; CHECK-X32-NEXT: cmpl $48, %eax
|
||||
; CHECK-X32-NEXT: jae .LBB0_25
|
||||
; CHECK-X32-NEXT: # %bb.24: # %entry
|
||||
; CHECK-X32-NEXT: addl $8, %eax
|
||||
; CHECK-X32-NEXT: movl %eax, (%esp)
|
||||
; CHECK-X32-NEXT: jmp .LBB0_26
|
||||
; CHECK-X32-NEXT: .LBB0_25: # %entry
|
||||
; CHECK-X32-NEXT: movl 8(%esp), %eax
|
||||
; CHECK-X32-NEXT: addl $8, %eax
|
||||
; CHECK-X32-NEXT: movl %eax, 8(%esp)
|
||||
; CHECK-X32-NEXT: .LBB0_26: # %entry
|
||||
; CHECK-X32-NEXT: movl 16(%esp), %ecx
|
||||
; CHECK-X32-NEXT: cmpl $48, %ecx
|
||||
; CHECK-X32-NEXT: jae .LBB0_28
|
||||
; CHECK-X32-NEXT: # %bb.27: # %entry
|
||||
; CHECK-X32-NEXT: movl 28(%esp), %eax
|
||||
; CHECK-X32-NEXT: addl %ecx, %eax
|
||||
; CHECK-X32-NEXT: addl $8, %ecx
|
||||
; CHECK-X32-NEXT: movl %ecx, 16(%esp)
|
||||
; CHECK-X32-NEXT: jmp .LBB0_29
|
||||
; CHECK-X32-NEXT: .LBB0_28: # %entry
|
||||
; CHECK-X32-NEXT: movl 24(%esp), %eax
|
||||
; CHECK-X32-NEXT: movl %eax, %ecx
|
||||
; CHECK-X32-NEXT: addl $8, %ecx
|
||||
; CHECK-X32-NEXT: movl %ecx, 24(%esp)
|
||||
; CHECK-X32-NEXT: .LBB0_29: # %entry
|
||||
; CHECK-X32-NEXT: movq (%eax), %rcx
|
||||
; CHECK-X32-NEXT: movl (%esp), %edx
|
||||
; CHECK-X32-NEXT: cmpl $48, %edx
|
||||
; CHECK-X32-NEXT: jae .LBB0_31
|
||||
; CHECK-X32-NEXT: # %bb.30: # %entry
|
||||
; CHECK-X32-NEXT: movl 12(%esp), %eax
|
||||
; CHECK-X32-NEXT: addl %edx, %eax
|
||||
; CHECK-X32-NEXT: addl $8, %edx
|
||||
; CHECK-X32-NEXT: movl %edx, (%esp)
|
||||
; CHECK-X32-NEXT: jmp .LBB0_32
|
||||
; CHECK-X32-NEXT: .LBB0_31: # %entry
|
||||
; CHECK-X32-NEXT: movl 8(%esp), %eax
|
||||
; CHECK-X32-NEXT: movl %eax, %edx
|
||||
; CHECK-X32-NEXT: addl $8, %edx
|
||||
; CHECK-X32-NEXT: movl %edx, 8(%esp)
|
||||
; CHECK-X32-NEXT: .LBB0_32: # %entry
|
||||
; CHECK-X32-NEXT: movl (%eax), %edx
|
||||
; CHECK-X32-NEXT: movl 16(%esp), %eax
|
||||
; CHECK-X32-NEXT: cmpl $48, %eax
|
||||
; CHECK-X32-NEXT: jae .LBB0_34
|
||||
; CHECK-X32-NEXT: # %bb.33: # %entry
|
||||
; CHECK-X32-NEXT: addl $8, %eax
|
||||
; CHECK-X32-NEXT: movl %eax, 16(%esp)
|
||||
; CHECK-X32-NEXT: jmp .LBB0_35
|
||||
; CHECK-X32-NEXT: .LBB0_34: # %entry
|
||||
; CHECK-X32-NEXT: movl 24(%esp), %eax
|
||||
; CHECK-X32-NEXT: addl $8, %eax
|
||||
; CHECK-X32-NEXT: movl %eax, 24(%esp)
|
||||
; CHECK-X32-NEXT: .LBB0_35: # %entry
|
||||
; CHECK-X32-NEXT: movl 4(%esp), %eax
|
||||
; CHECK-X32-NEXT: cmpl $176, %eax
|
||||
; CHECK-X32-NEXT: jae .LBB0_37
|
||||
; CHECK-X32-NEXT: # %bb.36: # %entry
|
||||
; CHECK-X32-NEXT: addl $16, %eax
|
||||
; CHECK-X32-NEXT: movl %eax, 4(%esp)
|
||||
; CHECK-X32-NEXT: jmp .LBB0_38
|
||||
; CHECK-X32-NEXT: .LBB0_37: # %entry
|
||||
; CHECK-X32-NEXT: movl 8(%esp), %eax
|
||||
; CHECK-X32-NEXT: addl $8, %eax
|
||||
; CHECK-X32-NEXT: movl %eax, 8(%esp)
|
||||
; CHECK-X32-NEXT: .LBB0_38: # %entry
|
||||
; CHECK-X32-NEXT: movl 20(%esp), %esi
|
||||
; CHECK-X32-NEXT: cmpl $176, %esi
|
||||
; CHECK-X32-NEXT: jae .LBB0_40
|
||||
; CHECK-X32-NEXT: # %bb.39: # %entry
|
||||
; CHECK-X32-NEXT: movl 28(%esp), %eax
|
||||
; CHECK-X32-NEXT: addl %esi, %eax
|
||||
; CHECK-X32-NEXT: addl $16, %esi
|
||||
; CHECK-X32-NEXT: movl %esi, 20(%esp)
|
||||
; CHECK-X32-NEXT: jmp .LBB0_41
|
||||
; CHECK-X32-NEXT: .LBB0_40: # %entry
|
||||
; CHECK-X32-NEXT: movl 24(%esp), %eax
|
||||
; CHECK-X32-NEXT: movl %eax, %esi
|
||||
; CHECK-X32-NEXT: addl $8, %esi
|
||||
; CHECK-X32-NEXT: movl %esi, 24(%esp)
|
||||
; CHECK-X32-NEXT: .LBB0_41: # %entry
|
||||
; CHECK-X32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
|
||||
; CHECK-X32-NEXT: movl (%esp), %esi
|
||||
; CHECK-X32-NEXT: cmpl $48, %esi
|
||||
; CHECK-X32-NEXT: jae .LBB0_43
|
||||
; CHECK-X32-NEXT: # %bb.42: # %entry
|
||||
; CHECK-X32-NEXT: movl 12(%esp), %eax
|
||||
; CHECK-X32-NEXT: addl %esi, %eax
|
||||
; CHECK-X32-NEXT: addl $8, %esi
|
||||
; CHECK-X32-NEXT: movl %esi, (%esp)
|
||||
; CHECK-X32-NEXT: jmp .LBB0_44
|
||||
; CHECK-X32-NEXT: .LBB0_43: # %entry
|
||||
; CHECK-X32-NEXT: movl 8(%esp), %eax
|
||||
; CHECK-X32-NEXT: movl %eax, %esi
|
||||
; CHECK-X32-NEXT: addl $8, %esi
|
||||
; CHECK-X32-NEXT: movl %esi, 8(%esp)
|
||||
; CHECK-X32-NEXT: .LBB0_44: # %entry
|
||||
; CHECK-X32-NEXT: movl (%eax), %esi
|
||||
; CHECK-X32-NEXT: movl 16(%esp), %eax
|
||||
; CHECK-X32-NEXT: cmpl $48, %eax
|
||||
; CHECK-X32-NEXT: jae .LBB0_46
|
||||
; CHECK-X32-NEXT: # %bb.45: # %entry
|
||||
; CHECK-X32-NEXT: addl $8, %eax
|
||||
; CHECK-X32-NEXT: movl %eax, 16(%esp)
|
||||
; CHECK-X32-NEXT: jmp .LBB0_47
|
||||
; CHECK-X32-NEXT: .LBB0_46: # %entry
|
||||
; CHECK-X32-NEXT: movl 24(%esp), %eax
|
||||
; CHECK-X32-NEXT: addl $8, %eax
|
||||
; CHECK-X32-NEXT: movl %eax, 24(%esp)
|
||||
; CHECK-X32-NEXT: .LBB0_47: # %entry
|
||||
; CHECK-X32-NEXT: movl $.str, %edi
|
||||
; CHECK-X32-NEXT: movb $2, %al
|
||||
; CHECK-X32-NEXT: pushq %r10
|
||||
; CHECK-X32-NEXT: pushq %r11
|
||||
; CHECK-X32-NEXT: callq printf@PLT
|
||||
; CHECK-X32-NEXT: addl $232, %esp
|
||||
; CHECK-X32-NEXT: retq
|
||||
entry:
|
||||
%ap1 = alloca %struct.va_list
|
||||
%ap2 = alloca %struct.va_list
|
||||
@ -320,6 +576,24 @@ define i32 @main() nounwind {
|
||||
; CHECK-X64-NEXT: xorl %eax, %eax
|
||||
; CHECK-X64-NEXT: popq %rcx
|
||||
; CHECK-X64-NEXT: retq
|
||||
;
|
||||
; CHECK-X32-LABEL: main:
|
||||
; CHECK-X32: # %bb.0: # %entry
|
||||
; CHECK-X32-NEXT: pushq %rax
|
||||
; CHECK-X32-NEXT: movl $12, (%esp)
|
||||
; CHECK-X32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
|
||||
; CHECK-X32-NEXT: movabsq $123456677890, %r8 # imm = 0x1CBE976802
|
||||
; CHECK-X32-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
|
||||
; CHECK-X32-NEXT: movl $1, %edi
|
||||
; CHECK-X32-NEXT: movl $2, %esi
|
||||
; CHECK-X32-NEXT: movl $3, %edx
|
||||
; CHECK-X32-NEXT: movl $-10, %ecx
|
||||
; CHECK-X32-NEXT: movl $120, %r9d
|
||||
; CHECK-X32-NEXT: movb $2, %al
|
||||
; CHECK-X32-NEXT: callq func
|
||||
; CHECK-X32-NEXT: xorl %eax, %eax
|
||||
; CHECK-X32-NEXT: popq %rcx
|
||||
; CHECK-X32-NEXT: retq
|
||||
entry:
|
||||
tail call void (...) @func(i32 1, i32 2, i32 3, double 4.500000e+15, i32 -10, i64 123456677890, i32 120, double 0x3FF3EB8520000000, i32 12) nounwind
|
||||
ret i32 0
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user