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R600: 3 op instructions have no write bit but the result are store in PV

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llvm-svn: 183111
This commit is contained in:
Vincent Lejeune 2013-06-03 15:56:12 +00:00
parent 97b4286f95
commit 991eb7f653
1 changed files with 1 additions and 3 deletions
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4
lib/Target/R600/R600Packetizer.cpp
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@ -80,9 +80,7 @@ private:
if (TII->isTransOnly(BI))
continue;
int OperandIdx = TII->getOperandIdx(BI->getOpcode(), R600Operands::WRITE);
if (OperandIdx < 0)
continue;
if (BI->getOperand(OperandIdx).getImm() == 0)
if (OperandIdx > -1 && BI->getOperand(OperandIdx).getImm() == 0)
continue;
unsigned Dst = BI->getOperand(0).getReg();
if (BI->getOpcode() == AMDGPU::DOT4_r600 ||