From 995d10cfeac6c42a31e5c04adb40d9f2292e31f2 Mon Sep 17 00:00:00 2001
From: Justin Holewinski <justin.holewinski@gmail.com>
Date: Mon, 14 Mar 2011 14:09:33 +0000
Subject: [PATCH] PTX: Add support for sqrt/sin/cos intrinsics

llvm-svn: 127578
---
 lib/Target/PTX/PTXInstrInfo.td     | 33 ++++++++++++++++++
 test/CodeGen/PTX/llvm-intrinsic.ll | 56 ++++++++++++++++++++++++++++++
 2 files changed, 89 insertions(+)
 create mode 100644 test/CodeGen/PTX/llvm-intrinsic.ll

diff --git a/lib/Target/PTX/PTXInstrInfo.td b/lib/Target/PTX/PTXInstrInfo.td
index a5f82f1bf38..5c198ca4826 100644
--- a/lib/Target/PTX/PTXInstrInfo.td
+++ b/lib/Target/PTX/PTXInstrInfo.td
@@ -414,6 +414,39 @@ def FDIVri64SM10 : InstPTX<(outs RRegf64:$d),
 // TODO: Allow the rounding mode to be selectable through llc.
 defm FMAD : PTX_FLOAT_4OP<"mad.rn", fmul, fadd>;
 
+///===- Floating-Point Intrinsic Instructions -----------------------------===//
+
+def FSQRT32 : InstPTX<(outs RRegf32:$d),
+                      (ins RRegf32:$a),
+                      "sqrt.rn.f32\t$d, $a",
+                      [(set RRegf32:$d, (fsqrt RRegf32:$a))]>;
+
+def FSQRT64 : InstPTX<(outs RRegf64:$d),
+                      (ins RRegf64:$a),
+                      "sqrt.rn.f64\t$d, $a",
+                      [(set RRegf64:$d, (fsqrt RRegf64:$a))]>;
+
+def FSIN32 : InstPTX<(outs RRegf32:$d),
+                     (ins RRegf32:$a),
+                     "sin.approx.f32\t$d, $a",
+                     [(set RRegf32:$d, (fsin RRegf32:$a))]>;
+
+def FSIN64 : InstPTX<(outs RRegf64:$d),
+                     (ins RRegf64:$a),
+                     "sin.approx.f64\t$d, $a",
+                     [(set RRegf64:$d, (fsin RRegf64:$a))]>;
+
+def FCOS32 : InstPTX<(outs RRegf32:$d),
+                     (ins RRegf32:$a),
+                     "cos.approx.f32\t$d, $a",
+                     [(set RRegf32:$d, (fcos RRegf32:$a))]>;
+
+def FCOS64 : InstPTX<(outs RRegf64:$d),
+                     (ins RRegf64:$a),
+                     "cos.approx.f64\t$d, $a",
+                     [(set RRegf64:$d, (fcos RRegf64:$a))]>;
+
+
 ///===- Comparison and Selection Instructions -----------------------------===//
 
 defm SETPEQu32 : PTX_SETP<RRegu32, "u32", i32imm, SETEQ,  "eq">;
diff --git a/test/CodeGen/PTX/llvm-intrinsic.ll b/test/CodeGen/PTX/llvm-intrinsic.ll
new file mode 100644
index 00000000000..3ce4c29f9f5
--- /dev/null
+++ b/test/CodeGen/PTX/llvm-intrinsic.ll
@@ -0,0 +1,56 @@
+; RUN: llc < %s -march=ptx -mattr=+ptx20,+sm20 | FileCheck %s
+
+define ptx_device float @test_sqrt_f32(float %x) {
+entry:
+; CHECK: sqrt.rn.f32 f0, f1;
+; CHECK-NEXT: ret;
+  %y = call float @llvm.sqrt.f32(float %x)
+  ret float %y
+}
+
+define ptx_device double @test_sqrt_f64(double %x) {
+entry:
+; CHECK: sqrt.rn.f64 fd0, fd1;
+; CHECK-NEXT: ret;
+  %y = call double @llvm.sqrt.f64(double %x)
+  ret double %y
+}
+
+define ptx_device float @test_sin_f32(float %x) {
+entry:
+; CHECK: sin.approx.f32 f0, f1;
+; CHECK-NEXT: ret;
+  %y = call float @llvm.sin.f32(float %x)
+  ret float %y
+}
+
+define ptx_device double @test_sin_f64(double %x) {
+entry:
+; CHECK: sin.approx.f64 fd0, fd1;
+; CHECK-NEXT: ret;
+  %y = call double @llvm.sin.f64(double %x)
+  ret double %y
+}
+
+define ptx_device float @test_cos_f32(float %x) {
+entry:
+; CHECK: cos.approx.f32 f0, f1;
+; CHECK-NEXT: ret;
+  %y = call float @llvm.cos.f32(float %x)
+  ret float %y
+}
+
+define ptx_device double @test_cos_f64(double %x) {
+entry:
+; CHECK: cos.approx.f64 fd0, fd1;
+; CHECK-NEXT: ret;
+  %y = call double @llvm.cos.f64(double %x)
+  ret double %y
+}
+
+declare float  @llvm.sqrt.f32(float)
+declare double @llvm.sqrt.f64(double)
+declare float  @llvm.sin.f32(float)
+declare double @llvm.sin.f64(double)
+declare float  @llvm.cos.f32(float)
+declare double @llvm.cos.f64(double)