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Make the same change to RegScavenger::backward.

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llvm-svn: 59566
This commit is contained in:
Evan Cheng 2008-11-18 23:54:01 +00:00
parent 5373c4c527
commit 997ba49e23
1 changed files with 28 additions and 9 deletions
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37
lib/CodeGen/RegisterScavenging.cpp
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@ -282,15 +282,38 @@ void RegScavenger::backward() {
MBBI = prior(MBBI);
MachineInstr *MI = MBBI;
// Process defs first.
const TargetInstrDesc &TID = MI->getDesc();
// Separate register operands into 3 classes: uses, defs, earlyclobbers.
SmallVector<std::pair<const MachineOperand*,unsigned>, 4> UseMOs;
SmallVector<std::pair<const MachineOperand*,unsigned>, 4> DefMOs;
SmallVector<std::pair<const MachineOperand*,unsigned>, 4> EarlyClobberMOs;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
if (!MO.isReg() || !MO.isDef())
if (!MO.isReg() || MO.getReg() == 0)
continue;
if (MO.isUse())
UseMOs.push_back(std::make_pair(&MO,i));
else if (MO.isEarlyClobber())
EarlyClobberMOs.push_back(std::make_pair(&MO,i));
else
DefMOs.push_back(std::make_pair(&MO,i));
}
// Process defs first.
unsigned NumECs = EarlyClobberMOs.size();
unsigned NumDefs = DefMOs.size();
for (unsigned i = 0, e = NumECs + NumDefs; i != e; ++i) {
const MachineOperand &MO = (i < NumDefs)
? *DefMOs[i].first : *EarlyClobberMOs[i-NumDefs].first;
unsigned Idx = (i < NumECs)
? DefMOs[i].second : EarlyClobberMOs[i-NumDefs].second;
// Skip two-address destination operand.
if (TID.findTiedToSrcOperand(i) != -1)
if (TID.findTiedToSrcOperand(Idx) != -1)
continue;
unsigned Reg = MO.getReg();
assert(isUsed(Reg));
if (!isReserved(Reg))
@ -299,13 +322,9 @@ void RegScavenger::backward() {
// Process uses.
BitVector UseRegs(NumPhysRegs);
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
if (!MO.isReg() || !MO.isUse())
continue;
for (unsigned i = 0, e = UseMOs.size(); i != e; ++i) {
const MachineOperand MO = *UseMOs[i].first;
unsigned Reg = MO.getReg();
if (Reg == 0)
continue;
assert(isUnused(Reg) || isReserved(Reg));
UseRegs.set(Reg);