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AMDGPU/GlobalISel: Select MUBUF path for global atomic cmpxchg
I'm not sure why this isn't a pattern, but the DAG manually selects this.
This commit is contained in:
Matt Arsenault
parent
1c6d7d0286
commit
9a28f067b2
@ -1659,6 +1659,65 @@ bool AMDGPUInstructionSelector::selectG_LOAD_ATOMICRMW(MachineInstr &I) const {
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return selectImpl(I, *CoverageInfo);
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return selectImpl(I, *CoverageInfo);
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}
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}
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// TODO: No rtn optimization.
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bool AMDGPUInstructionSelector::selectG_AMDGPU_ATOMIC_CMPXCHG(
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MachineInstr &MI) const {
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Register PtrReg = MI.getOperand(1).getReg();
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const LLT PtrTy = MRI->getType(PtrReg);
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if (PtrTy.getAddressSpace() == AMDGPUAS::FLAT_ADDRESS ||
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STI.useFlatForGlobal())
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return selectImpl(MI, *CoverageInfo);
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Register DstReg = MI.getOperand(0).getReg();
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const LLT Ty = MRI->getType(DstReg);
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const bool Is64 = Ty.getSizeInBits() == 64;
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const unsigned SubReg = Is64 ? AMDGPU::sub0_sub1 : AMDGPU::sub0;
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Register TmpReg = MRI->createVirtualRegister(
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Is64 ? &AMDGPU::VReg_128RegClass : &AMDGPU::VReg_64RegClass);
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const DebugLoc &DL = MI.getDebugLoc();
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MachineBasicBlock *BB = MI.getParent();
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Register VAddr, RSrcReg, SOffset;
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int64_t Offset = 0;
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unsigned Opcode;
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if (selectMUBUFOffsetImpl(MI.getOperand(1), RSrcReg, SOffset, Offset)) {
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Opcode = Is64 ? AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN :
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AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN;
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} else if (selectMUBUFAddr64Impl(MI.getOperand(1), VAddr,
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RSrcReg, SOffset, Offset)) {
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Opcode = Is64 ? AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN :
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AMDGPU::BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN;
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} else
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return selectImpl(MI, *CoverageInfo);
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auto MIB = BuildMI(*BB, &MI, DL, TII.get(Opcode), TmpReg)
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.addReg(MI.getOperand(2).getReg());
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if (VAddr)
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MIB.addReg(VAddr);
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MIB.addReg(RSrcReg);
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if (SOffset)
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MIB.addReg(SOffset);
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else
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MIB.addImm(0);
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MIB.addImm(Offset);
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MIB.addImm(0); // slc
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MIB.cloneMemRefs(MI);
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BuildMI(*BB, &MI, DL, TII.get(AMDGPU::COPY), DstReg)
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.addReg(TmpReg, RegState::Kill, SubReg);
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MI.eraseFromParent();
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MRI->setRegClass(
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DstReg, Is64 ? &AMDGPU::VReg_64RegClass : &AMDGPU::VGPR_32RegClass);
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return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
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}
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bool AMDGPUInstructionSelector::selectG_BRCOND(MachineInstr &I) const {
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bool AMDGPUInstructionSelector::selectG_BRCOND(MachineInstr &I) const {
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MachineBasicBlock *BB = I.getParent();
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MachineBasicBlock *BB = I.getParent();
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MachineOperand &CondOp = I.getOperand(0);
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MachineOperand &CondOp = I.getOperand(0);
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@ -2031,6 +2090,8 @@ bool AMDGPUInstructionSelector::select(MachineInstr &I) {
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case TargetOpcode::G_ATOMICRMW_UMAX:
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case TargetOpcode::G_ATOMICRMW_UMAX:
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case TargetOpcode::G_ATOMICRMW_FADD:
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case TargetOpcode::G_ATOMICRMW_FADD:
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return selectG_LOAD_ATOMICRMW(I);
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return selectG_LOAD_ATOMICRMW(I);
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case AMDGPU::G_AMDGPU_ATOMIC_CMPXCHG:
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return selectG_AMDGPU_ATOMIC_CMPXCHG(I);
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case TargetOpcode::G_SELECT:
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case TargetOpcode::G_SELECT:
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return selectG_SELECT(I);
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return selectG_SELECT(I);
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case TargetOpcode::G_STORE:
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case TargetOpcode::G_STORE:
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@ -116,6 +116,7 @@ private:
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void initM0(MachineInstr &I) const;
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void initM0(MachineInstr &I) const;
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bool selectG_LOAD_ATOMICRMW(MachineInstr &I) const;
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bool selectG_LOAD_ATOMICRMW(MachineInstr &I) const;
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bool selectG_AMDGPU_ATOMIC_CMPXCHG(MachineInstr &I) const;
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bool selectG_STORE(MachineInstr &I) const;
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bool selectG_STORE(MachineInstr &I) const;
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bool selectG_SELECT(MachineInstr &I) const;
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bool selectG_SELECT(MachineInstr &I) const;
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bool selectG_BRCOND(MachineInstr &I) const;
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bool selectG_BRCOND(MachineInstr &I) const;
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@ -0,0 +1,826 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s
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# RUN: llc -march=amdgcn -mcpu=hawaii -mattr=-flat-for-global -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX7 %s
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# RUN: llc -march=amdgcn -mcpu=hawaii -mattr=+flat-for-global -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX7-FLAT %s
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX8 %s
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# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s
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# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX10 %s
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---
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name: amdgpu_atomic_cmpxchg_s32_global
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3
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; GFX6-LABEL: name: amdgpu_atomic_cmpxchg_s32_global
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; GFX6: liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3
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; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
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; GFX6: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1
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; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
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; GFX6: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440
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; GFX6: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
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; GFX6: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
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; GFX6: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3
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; GFX6: [[BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN [[REG_SEQUENCE]], [[COPY]], [[REG_SEQUENCE2]], 0, 0, 0, implicit $exec :: (load store seq_cst 4, addrspace 1)
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; GFX6: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN]].sub0
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; GFX6: $vgpr0 = COPY [[COPY3]]
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; GFX7-LABEL: name: amdgpu_atomic_cmpxchg_s32_global
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; GFX7: liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3
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; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
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; GFX7: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1
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; GFX7: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
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; GFX7: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440
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; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
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; GFX7: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
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; GFX7: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3
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; GFX7: [[BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN [[REG_SEQUENCE]], [[COPY]], [[REG_SEQUENCE2]], 0, 0, 0, implicit $exec :: (load store seq_cst 4, addrspace 1)
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; GFX7: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN]].sub0
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; GFX7: $vgpr0 = COPY [[COPY3]]
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; GFX7-FLAT-LABEL: name: amdgpu_atomic_cmpxchg_s32_global
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; GFX7-FLAT: liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3
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; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; GFX7-FLAT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; GFX7-FLAT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
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; GFX7-FLAT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1
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; GFX7-FLAT: [[FLAT_ATOMIC_CMPSWAP_RTN:%[0-9]+]]:vgpr_32 = FLAT_ATOMIC_CMPSWAP_RTN [[COPY]], [[REG_SEQUENCE]], 0, 0, implicit $exec, implicit $flat_scr :: (load store seq_cst 4, addrspace 1)
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; GFX7-FLAT: $vgpr0 = COPY [[FLAT_ATOMIC_CMPSWAP_RTN]]
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; GFX8-LABEL: name: amdgpu_atomic_cmpxchg_s32_global
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; GFX8: liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3
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; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
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; GFX8: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1
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; GFX8: [[FLAT_ATOMIC_CMPSWAP_RTN:%[0-9]+]]:vgpr_32 = FLAT_ATOMIC_CMPSWAP_RTN [[COPY]], [[REG_SEQUENCE]], 0, 0, implicit $exec, implicit $flat_scr :: (load store seq_cst 4, addrspace 1)
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; GFX8: $vgpr0 = COPY [[FLAT_ATOMIC_CMPSWAP_RTN]]
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; GFX9-LABEL: name: amdgpu_atomic_cmpxchg_s32_global
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; GFX9: liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3
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; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
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; GFX9: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1
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; GFX9: [[GLOBAL_ATOMIC_CMPSWAP_RTN:%[0-9]+]]:vgpr_32 = GLOBAL_ATOMIC_CMPSWAP_RTN [[COPY]], [[REG_SEQUENCE]], 0, 0, implicit $exec :: (load store seq_cst 4, addrspace 1)
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; GFX9: $vgpr0 = COPY [[GLOBAL_ATOMIC_CMPSWAP_RTN]]
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; GFX10-LABEL: name: amdgpu_atomic_cmpxchg_s32_global
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; GFX10: liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3
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; GFX10: $vcc_hi = IMPLICIT_DEF
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; GFX10: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
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; GFX10: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1
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; GFX10: [[GLOBAL_ATOMIC_CMPSWAP_RTN:%[0-9]+]]:vgpr_32 = GLOBAL_ATOMIC_CMPSWAP_RTN [[COPY]], [[REG_SEQUENCE]], 0, 0, implicit $exec :: (load store seq_cst 4, addrspace 1)
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; GFX10: $vgpr0 = COPY [[GLOBAL_ATOMIC_CMPSWAP_RTN]]
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%0:vgpr(p1) = COPY $vgpr0_vgpr1
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%1:vgpr(s32) = COPY $vgpr2
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%2:vgpr(s32) = COPY $vgpr3
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%3:vgpr(<2 x s32>) = G_BUILD_VECTOR %1, %2
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%4:vgpr(s32) = G_AMDGPU_ATOMIC_CMPXCHG %0, %3 :: (load store seq_cst 4, addrspace 1)
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$vgpr0 = COPY %4
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...
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---
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name: amdgpu_atomic_cmpxchg_s32_global_gep4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3
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; GFX6-LABEL: name: amdgpu_atomic_cmpxchg_s32_global_gep4
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; GFX6: liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3
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; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
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; GFX6: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1
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; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
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; GFX6: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440
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; GFX6: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
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; GFX6: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
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; GFX6: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3
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; GFX6: [[BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN [[REG_SEQUENCE]], [[COPY]], [[REG_SEQUENCE2]], 0, 4, 0, implicit $exec :: (load store seq_cst 4, addrspace 1)
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; GFX6: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN]].sub0
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; GFX6: $vgpr0 = COPY [[COPY3]]
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; GFX7-LABEL: name: amdgpu_atomic_cmpxchg_s32_global_gep4
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; GFX7: liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3
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; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
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; GFX7: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1
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; GFX7: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
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; GFX7: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440
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; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
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; GFX7: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
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; GFX7: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3
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; GFX7: [[BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN [[REG_SEQUENCE]], [[COPY]], [[REG_SEQUENCE2]], 0, 4, 0, implicit $exec :: (load store seq_cst 4, addrspace 1)
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; GFX7: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN]].sub0
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; GFX7: $vgpr0 = COPY [[COPY3]]
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; GFX7-FLAT-LABEL: name: amdgpu_atomic_cmpxchg_s32_global_gep4
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|
; GFX7-FLAT: liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3
|
||||||
|
; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||||
|
; GFX7-FLAT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||||
|
; GFX7-FLAT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
|
||||||
|
; GFX7-FLAT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1
|
||||||
|
; GFX7-FLAT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4, implicit $exec
|
||||||
|
; GFX7-FLAT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
||||||
|
; GFX7-FLAT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1
|
||||||
|
; GFX7-FLAT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
|
||||||
|
; GFX7-FLAT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0
|
||||||
|
; GFX7-FLAT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
|
||||||
|
; GFX7-FLAT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1
|
||||||
|
; GFX7-FLAT: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY3]], [[COPY4]], 0, implicit $exec
|
||||||
|
; GFX7-FLAT: %12:vgpr_32, dead %14:sreg_64_xexec = V_ADDC_U32_e64 [[COPY5]], [[COPY6]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec
|
||||||
|
; GFX7-FLAT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %12, %subreg.sub1
|
||||||
|
; GFX7-FLAT: [[FLAT_ATOMIC_CMPSWAP_RTN:%[0-9]+]]:vgpr_32 = FLAT_ATOMIC_CMPSWAP_RTN [[REG_SEQUENCE2]], [[REG_SEQUENCE]], 0, 0, implicit $exec, implicit $flat_scr :: (load store seq_cst 4, addrspace 1)
|
||||||
|
; GFX7-FLAT: $vgpr0 = COPY [[FLAT_ATOMIC_CMPSWAP_RTN]]
|
||||||
|
; GFX8-LABEL: name: amdgpu_atomic_cmpxchg_s32_global_gep4
|
||||||
|
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3
|
||||||
|
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||||
|
; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||||
|
; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
|
||||||
|
; GFX8: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1
|
||||||
|
; GFX8: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4, implicit $exec
|
||||||
|
; GFX8: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
||||||
|
; GFX8: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1
|
||||||
|
; GFX8: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
|
||||||
|
; GFX8: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0
|
||||||
|
; GFX8: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
|
||||||
|
; GFX8: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1
|
||||||
|
; GFX8: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY3]], [[COPY4]], 0, implicit $exec
|
||||||
|
; GFX8: %12:vgpr_32, dead %14:sreg_64_xexec = V_ADDC_U32_e64 [[COPY5]], [[COPY6]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec
|
||||||
|
; GFX8: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %12, %subreg.sub1
|
||||||
|
; GFX8: [[FLAT_ATOMIC_CMPSWAP_RTN:%[0-9]+]]:vgpr_32 = FLAT_ATOMIC_CMPSWAP_RTN [[REG_SEQUENCE2]], [[REG_SEQUENCE]], 0, 0, implicit $exec, implicit $flat_scr :: (load store seq_cst 4, addrspace 1)
|
||||||
|
; GFX8: $vgpr0 = COPY [[FLAT_ATOMIC_CMPSWAP_RTN]]
|
||||||
|
; GFX9-LABEL: name: amdgpu_atomic_cmpxchg_s32_global_gep4
|
||||||
|
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3
|
||||||
|
; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||||
|
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||||
|
; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
|
||||||
|
; GFX9: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1
|
||||||
|
; GFX9: [[GLOBAL_ATOMIC_CMPSWAP_RTN:%[0-9]+]]:vgpr_32 = GLOBAL_ATOMIC_CMPSWAP_RTN [[COPY]], [[REG_SEQUENCE]], 4, 0, implicit $exec :: (load store seq_cst 4, addrspace 1)
|
||||||
|
; GFX9: $vgpr0 = COPY [[GLOBAL_ATOMIC_CMPSWAP_RTN]]
|
||||||
|
; GFX10-LABEL: name: amdgpu_atomic_cmpxchg_s32_global_gep4
|
||||||
|
; GFX10: liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3
|
||||||
|
; GFX10: $vcc_hi = IMPLICIT_DEF
|
||||||
|
; GFX10: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||||
|
; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||||
|
; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
|
||||||
|
; GFX10: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1
|
||||||
|
; GFX10: [[GLOBAL_ATOMIC_CMPSWAP_RTN:%[0-9]+]]:vgpr_32 = GLOBAL_ATOMIC_CMPSWAP_RTN [[COPY]], [[REG_SEQUENCE]], 4, 0, implicit $exec :: (load store seq_cst 4, addrspace 1)
|
||||||
|
; GFX10: $vgpr0 = COPY [[GLOBAL_ATOMIC_CMPSWAP_RTN]]
|
||||||
|
%0:vgpr(p1) = COPY $vgpr0_vgpr1
|
||||||
|
%1:vgpr(s32) = COPY $vgpr2
|
||||||
|
%2:vgpr(s32) = COPY $vgpr3
|
||||||
|
%3:vgpr(<2 x s32>) = G_BUILD_VECTOR %1, %2
|
||||||
|
%4:vgpr(s64) = G_CONSTANT i64 4
|
||||||
|
%5:vgpr(p1) = G_PTR_ADD %0, %4
|
||||||
|
%6:vgpr(s32) = G_AMDGPU_ATOMIC_CMPXCHG %5, %3 :: (load store seq_cst 4, addrspace 1)
|
||||||
|
$vgpr0 = COPY %6
|
||||||
|
|
||||||
|
...
|
||||||
|
|
||||||
|
---
|
||||||
|
name: amdgpu_atomic_cmpxchg_s64_global
|
||||||
|
legalized: true
|
||||||
|
regBankSelected: true
|
||||||
|
tracksRegLiveness: true
|
||||||
|
body: |
|
||||||
|
bb.0:
|
||||||
|
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
|
||||||
|
|
||||||
|
; GFX6-LABEL: name: amdgpu_atomic_cmpxchg_s64_global
|
||||||
|
; GFX6: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
|
||||||
|
; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||||
|
; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||||
|
; GFX6: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr4_vgpr5
|
||||||
|
; GFX6: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0_sub1, [[COPY2]], %subreg.sub2_sub3
|
||||||
|
; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
|
||||||
|
; GFX6: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440
|
||||||
|
; GFX6: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
|
||||||
|
; GFX6: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
|
||||||
|
; GFX6: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3
|
||||||
|
; GFX6: [[BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN [[REG_SEQUENCE]], [[COPY]], [[REG_SEQUENCE2]], 0, 0, 0, implicit $exec :: (load store seq_cst 8, addrspace 1)
|
||||||
|
; GFX6: [[COPY3:%[0-9]+]]:vreg_64 = COPY killed [[BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN]].sub0_sub1
|
||||||
|
; GFX6: $vgpr0_vgpr1 = COPY [[COPY3]]
|
||||||
|
; GFX7-LABEL: name: amdgpu_atomic_cmpxchg_s64_global
|
||||||
|
; GFX7: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
|
||||||
|
; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||||
|
; GFX7: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||||
|
; GFX7: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr4_vgpr5
|
||||||
|
; GFX7: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0_sub1, [[COPY2]], %subreg.sub2_sub3
|
||||||
|
; GFX7: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
|
||||||
|
; GFX7: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440
|
||||||
|
; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
|
||||||
|
; GFX7: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
|
||||||
|
; GFX7: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3
|
||||||
|
; GFX7: [[BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN [[REG_SEQUENCE]], [[COPY]], [[REG_SEQUENCE2]], 0, 0, 0, implicit $exec :: (load store seq_cst 8, addrspace 1)
|
||||||
|
; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY killed [[BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN]].sub0_sub1
|
||||||
|
; GFX7: $vgpr0_vgpr1 = COPY [[COPY3]]
|
||||||
|
; GFX7-FLAT-LABEL: name: amdgpu_atomic_cmpxchg_s64_global
|
||||||
|
; GFX7-FLAT: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
|
||||||
|
; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||||
|
; GFX7-FLAT: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||||
|
; GFX7-FLAT: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr4_vgpr5
|
||||||
|
; GFX7-FLAT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0_sub1, [[COPY2]], %subreg.sub2_sub3
|
||||||
|
; GFX7-FLAT: [[FLAT_ATOMIC_CMPSWAP_X2_RTN:%[0-9]+]]:vreg_64 = FLAT_ATOMIC_CMPSWAP_X2_RTN [[COPY]], [[REG_SEQUENCE]], 0, 0, implicit $exec, implicit $flat_scr :: (load store seq_cst 8, addrspace 1)
|
||||||
|
; GFX7-FLAT: $vgpr0_vgpr1 = COPY [[FLAT_ATOMIC_CMPSWAP_X2_RTN]]
|
||||||
|
; GFX8-LABEL: name: amdgpu_atomic_cmpxchg_s64_global
|
||||||
|
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
|
||||||
|
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||||
|
; GFX8: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||||
|
; GFX8: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr4_vgpr5
|
||||||
|
; GFX8: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0_sub1, [[COPY2]], %subreg.sub2_sub3
|
||||||
|
; GFX8: [[FLAT_ATOMIC_CMPSWAP_X2_RTN:%[0-9]+]]:vreg_64 = FLAT_ATOMIC_CMPSWAP_X2_RTN [[COPY]], [[REG_SEQUENCE]], 0, 0, implicit $exec, implicit $flat_scr :: (load store seq_cst 8, addrspace 1)
|
||||||
|
; GFX8: $vgpr0_vgpr1 = COPY [[FLAT_ATOMIC_CMPSWAP_X2_RTN]]
|
||||||
|
; GFX9-LABEL: name: amdgpu_atomic_cmpxchg_s64_global
|
||||||
|
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
|
||||||
|
; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||||
|
; GFX9: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||||
|
; GFX9: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr4_vgpr5
|
||||||
|
; GFX9: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0_sub1, [[COPY2]], %subreg.sub2_sub3
|
||||||
|
; GFX9: [[GLOBAL_ATOMIC_CMPSWAP_X2_RTN:%[0-9]+]]:vreg_64 = GLOBAL_ATOMIC_CMPSWAP_X2_RTN [[COPY]], [[REG_SEQUENCE]], 0, 0, implicit $exec :: (load store seq_cst 8, addrspace 1)
|
||||||
|
; GFX9: $vgpr0_vgpr1 = COPY [[GLOBAL_ATOMIC_CMPSWAP_X2_RTN]]
|
||||||
|
; GFX10-LABEL: name: amdgpu_atomic_cmpxchg_s64_global
|
||||||
|
; GFX10: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
|
||||||
|
; GFX10: $vcc_hi = IMPLICIT_DEF
|
||||||
|
; GFX10: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||||
|
; GFX10: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||||
|
; GFX10: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr4_vgpr5
|
||||||
|
; GFX10: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0_sub1, [[COPY2]], %subreg.sub2_sub3
|
||||||
|
; GFX10: [[GLOBAL_ATOMIC_CMPSWAP_X2_RTN:%[0-9]+]]:vreg_64 = GLOBAL_ATOMIC_CMPSWAP_X2_RTN [[COPY]], [[REG_SEQUENCE]], 0, 0, implicit $exec :: (load store seq_cst 8, addrspace 1)
|
||||||
|
; GFX10: $vgpr0_vgpr1 = COPY [[GLOBAL_ATOMIC_CMPSWAP_X2_RTN]]
|
||||||
|
%0:vgpr(p1) = COPY $vgpr0_vgpr1
|
||||||
|
%1:vgpr(s64) = COPY $vgpr2_vgpr3
|
||||||
|
%2:vgpr(s64) = COPY $vgpr4_vgpr5
|
||||||
|
%3:vgpr(<2 x s64>) = G_BUILD_VECTOR %1, %2
|
||||||
|
%4:vgpr(s64) = G_AMDGPU_ATOMIC_CMPXCHG %0, %3 :: (load store seq_cst 8, addrspace 1)
|
||||||
|
$vgpr0_vgpr1 = COPY %4
|
||||||
|
|
||||||
|
...
|
||||||
|
|
||||||
|
---
|
||||||
|
name: amdgpu_atomic_cmpxchg_s64_global_gep4
|
||||||
|
legalized: true
|
||||||
|
regBankSelected: true
|
||||||
|
tracksRegLiveness: true
|
||||||
|
body: |
|
||||||
|
bb.0:
|
||||||
|
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
|
||||||
|
|
||||||
|
; GFX6-LABEL: name: amdgpu_atomic_cmpxchg_s64_global_gep4
|
||||||
|
; GFX6: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
|
||||||
|
; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||||
|
; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||||
|
; GFX6: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr4_vgpr5
|
||||||
|
; GFX6: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0_sub1, [[COPY2]], %subreg.sub2_sub3
|
||||||
|
; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
|
||||||
|
; GFX6: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440
|
||||||
|
; GFX6: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
|
||||||
|
; GFX6: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
|
||||||
|
; GFX6: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3
|
||||||
|
; GFX6: [[BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN [[REG_SEQUENCE]], [[COPY]], [[REG_SEQUENCE2]], 0, 4, 0, implicit $exec :: (load store seq_cst 8, addrspace 1)
|
||||||
|
; GFX6: [[COPY3:%[0-9]+]]:vreg_64 = COPY killed [[BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN]].sub0_sub1
|
||||||
|
; GFX6: $vgpr0_vgpr1 = COPY [[COPY3]]
|
||||||
|
; GFX7-LABEL: name: amdgpu_atomic_cmpxchg_s64_global_gep4
|
||||||
|
; GFX7: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
|
||||||
|
; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||||
|
; GFX7: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||||
|
; GFX7: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr4_vgpr5
|
||||||
|
; GFX7: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0_sub1, [[COPY2]], %subreg.sub2_sub3
|
||||||
|
; GFX7: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
|
||||||
|
; GFX7: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440
|
||||||
|
; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
|
||||||
|
; GFX7: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
|
||||||
|
; GFX7: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3
|
||||||
|
; GFX7: [[BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN [[REG_SEQUENCE]], [[COPY]], [[REG_SEQUENCE2]], 0, 4, 0, implicit $exec :: (load store seq_cst 8, addrspace 1)
|
||||||
|
; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY killed [[BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN]].sub0_sub1
|
||||||
|
; GFX7: $vgpr0_vgpr1 = COPY [[COPY3]]
|
||||||
|
; GFX7-FLAT-LABEL: name: amdgpu_atomic_cmpxchg_s64_global_gep4
|
||||||
|
; GFX7-FLAT: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
|
||||||
|
; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||||
|
; GFX7-FLAT: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||||
|
; GFX7-FLAT: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr4_vgpr5
|
||||||
|
; GFX7-FLAT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0_sub1, [[COPY2]], %subreg.sub2_sub3
|
||||||
|
; GFX7-FLAT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4, implicit $exec
|
||||||
|
; GFX7-FLAT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
||||||
|
; GFX7-FLAT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1
|
||||||
|
; GFX7-FLAT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
|
||||||
|
; GFX7-FLAT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0
|
||||||
|
; GFX7-FLAT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
|
||||||
|
; GFX7-FLAT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1
|
||||||
|
; GFX7-FLAT: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY3]], [[COPY4]], 0, implicit $exec
|
||||||
|
; GFX7-FLAT: %12:vgpr_32, dead %14:sreg_64_xexec = V_ADDC_U32_e64 [[COPY5]], [[COPY6]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec
|
||||||
|
; GFX7-FLAT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %12, %subreg.sub1
|
||||||
|
; GFX7-FLAT: [[FLAT_ATOMIC_CMPSWAP_X2_RTN:%[0-9]+]]:vreg_64 = FLAT_ATOMIC_CMPSWAP_X2_RTN [[REG_SEQUENCE2]], [[REG_SEQUENCE]], 0, 0, implicit $exec, implicit $flat_scr :: (load store seq_cst 8, addrspace 1)
|
||||||
|
; GFX7-FLAT: $vgpr0_vgpr1 = COPY [[FLAT_ATOMIC_CMPSWAP_X2_RTN]]
|
||||||
|
; GFX8-LABEL: name: amdgpu_atomic_cmpxchg_s64_global_gep4
|
||||||
|
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
|
||||||
|
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||||
|
; GFX8: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||||
|
; GFX8: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr4_vgpr5
|
||||||
|
; GFX8: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0_sub1, [[COPY2]], %subreg.sub2_sub3
|
||||||
|
; GFX8: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4, implicit $exec
|
||||||
|
; GFX8: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
||||||
|
; GFX8: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1
|
||||||
|
; GFX8: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
|
||||||
|
; GFX8: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0
|
||||||
|
; GFX8: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
|
||||||
|
; GFX8: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1
|
||||||
|
; GFX8: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY3]], [[COPY4]], 0, implicit $exec
|
||||||
|
; GFX8: %12:vgpr_32, dead %14:sreg_64_xexec = V_ADDC_U32_e64 [[COPY5]], [[COPY6]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec
|
||||||
|
; GFX8: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %12, %subreg.sub1
|
||||||
|
; GFX8: [[FLAT_ATOMIC_CMPSWAP_X2_RTN:%[0-9]+]]:vreg_64 = FLAT_ATOMIC_CMPSWAP_X2_RTN [[REG_SEQUENCE2]], [[REG_SEQUENCE]], 0, 0, implicit $exec, implicit $flat_scr :: (load store seq_cst 8, addrspace 1)
|
||||||
|
; GFX8: $vgpr0_vgpr1 = COPY [[FLAT_ATOMIC_CMPSWAP_X2_RTN]]
|
||||||
|
; GFX9-LABEL: name: amdgpu_atomic_cmpxchg_s64_global_gep4
|
||||||
|
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
|
||||||
|
; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||||
|
; GFX9: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||||
|
; GFX9: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr4_vgpr5
|
||||||
|
; GFX9: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0_sub1, [[COPY2]], %subreg.sub2_sub3
|
||||||
|
; GFX9: [[GLOBAL_ATOMIC_CMPSWAP_X2_RTN:%[0-9]+]]:vreg_64 = GLOBAL_ATOMIC_CMPSWAP_X2_RTN [[COPY]], [[REG_SEQUENCE]], 4, 0, implicit $exec :: (load store seq_cst 8, addrspace 1)
|
||||||
|
; GFX9: $vgpr0_vgpr1 = COPY [[GLOBAL_ATOMIC_CMPSWAP_X2_RTN]]
|
||||||
|
; GFX10-LABEL: name: amdgpu_atomic_cmpxchg_s64_global_gep4
|
||||||
|
; GFX10: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
|
||||||
|
; GFX10: $vcc_hi = IMPLICIT_DEF
|
||||||
|
; GFX10: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||||
|
; GFX10: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||||
|
; GFX10: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr4_vgpr5
|
||||||
|
; GFX10: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0_sub1, [[COPY2]], %subreg.sub2_sub3
|
||||||
|
; GFX10: [[GLOBAL_ATOMIC_CMPSWAP_X2_RTN:%[0-9]+]]:vreg_64 = GLOBAL_ATOMIC_CMPSWAP_X2_RTN [[COPY]], [[REG_SEQUENCE]], 4, 0, implicit $exec :: (load store seq_cst 8, addrspace 1)
|
||||||
|
; GFX10: $vgpr0_vgpr1 = COPY [[GLOBAL_ATOMIC_CMPSWAP_X2_RTN]]
|
||||||
|
%0:vgpr(p1) = COPY $vgpr0_vgpr1
|
||||||
|
%1:vgpr(s64) = COPY $vgpr2_vgpr3
|
||||||
|
%2:vgpr(s64) = COPY $vgpr4_vgpr5
|
||||||
|
%3:vgpr(<2 x s64>) = G_BUILD_VECTOR %1, %2
|
||||||
|
%4:vgpr(s64) = G_CONSTANT i64 4
|
||||||
|
%5:vgpr(p1) = G_PTR_ADD %0, %4
|
||||||
|
%6:vgpr(s64) = G_AMDGPU_ATOMIC_CMPXCHG %5, %3 :: (load store seq_cst 8, addrspace 1)
|
||||||
|
$vgpr0_vgpr1 = COPY %6
|
||||||
|
|
||||||
|
...
|
||||||
|
|
||||||
|
---
|
||||||
|
name: amdgpu_atomic_cmpxchg_s32_global_gepm4
|
||||||
|
legalized: true
|
||||||
|
regBankSelected: true
|
||||||
|
tracksRegLiveness: true
|
||||||
|
body: |
|
||||||
|
bb.0:
|
||||||
|
liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3
|
||||||
|
|
||||||
|
; GFX6-LABEL: name: amdgpu_atomic_cmpxchg_s32_global_gepm4
|
||||||
|
; GFX6: liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3
|
||||||
|
; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||||
|
; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||||
|
; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
|
||||||
|
; GFX6: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1
|
||||||
|
; GFX6: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294967292, implicit $exec
|
||||||
|
; GFX6: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
|
||||||
|
; GFX6: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1
|
||||||
|
; GFX6: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
|
||||||
|
; GFX6: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0
|
||||||
|
; GFX6: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
|
||||||
|
; GFX6: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1
|
||||||
|
; GFX6: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY3]], [[COPY4]], 0, implicit $exec
|
||||||
|
; GFX6: %18:vgpr_32, dead %20:sreg_64_xexec = V_ADDC_U32_e64 [[COPY5]], [[COPY6]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec
|
||||||
|
; GFX6: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %18, %subreg.sub1
|
||||||
|
; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
|
||||||
|
; GFX6: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440
|
||||||
|
; GFX6: [[REG_SEQUENCE3:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
|
||||||
|
; GFX6: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
|
||||||
|
; GFX6: [[REG_SEQUENCE4:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE3]], %subreg.sub2_sub3
|
||||||
|
; GFX6: [[BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE4]], 0, 0, 0, implicit $exec :: (load store seq_cst 4, addrspace 1)
|
||||||
|
; GFX6: [[COPY7:%[0-9]+]]:vgpr_32 = COPY killed [[BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN]].sub0
|
||||||
|
; GFX6: $vgpr0 = COPY [[COPY7]]
|
||||||
|
; GFX7-LABEL: name: amdgpu_atomic_cmpxchg_s32_global_gepm4
|
||||||
|
; GFX7: liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3
|
||||||
|
; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||||
|
; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||||
|
; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
|
||||||
|
; GFX7: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1
|
||||||
|
; GFX7: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294967292, implicit $exec
|
||||||
|
; GFX7: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
|
||||||
|
; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1
|
||||||
|
; GFX7: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
|
||||||
|
; GFX7: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0
|
||||||
|
; GFX7: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
|
||||||
|
; GFX7: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1
|
||||||
|
; GFX7: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY3]], [[COPY4]], 0, implicit $exec
|
||||||
|
; GFX7: %18:vgpr_32, dead %20:sreg_64_xexec = V_ADDC_U32_e64 [[COPY5]], [[COPY6]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec
|
||||||
|
; GFX7: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %18, %subreg.sub1
|
||||||
|
; GFX7: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
|
||||||
|
; GFX7: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440
|
||||||
|
; GFX7: [[REG_SEQUENCE3:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
|
||||||
|
; GFX7: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
|
||||||
|
; GFX7: [[REG_SEQUENCE4:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE3]], %subreg.sub2_sub3
|
||||||
|
; GFX7: [[BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE4]], 0, 0, 0, implicit $exec :: (load store seq_cst 4, addrspace 1)
|
||||||
|
; GFX7: [[COPY7:%[0-9]+]]:vgpr_32 = COPY killed [[BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN]].sub0
|
||||||
|
; GFX7: $vgpr0 = COPY [[COPY7]]
|
||||||
|
; GFX7-FLAT-LABEL: name: amdgpu_atomic_cmpxchg_s32_global_gepm4
|
||||||
|
; GFX7-FLAT: liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3
|
||||||
|
; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||||
|
; GFX7-FLAT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||||
|
; GFX7-FLAT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
|
||||||
|
; GFX7-FLAT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1
|
||||||
|
; GFX7-FLAT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294967292, implicit $exec
|
||||||
|
; GFX7-FLAT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
|
||||||
|
; GFX7-FLAT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1
|
||||||
|
; GFX7-FLAT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
|
||||||
|
; GFX7-FLAT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0
|
||||||
|
; GFX7-FLAT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
|
||||||
|
; GFX7-FLAT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1
|
||||||
|
; GFX7-FLAT: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY3]], [[COPY4]], 0, implicit $exec
|
||||||
|
; GFX7-FLAT: %12:vgpr_32, dead %14:sreg_64_xexec = V_ADDC_U32_e64 [[COPY5]], [[COPY6]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec
|
||||||
|
; GFX7-FLAT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %12, %subreg.sub1
|
||||||
|
; GFX7-FLAT: [[FLAT_ATOMIC_CMPSWAP_RTN:%[0-9]+]]:vgpr_32 = FLAT_ATOMIC_CMPSWAP_RTN [[REG_SEQUENCE2]], [[REG_SEQUENCE]], 0, 0, implicit $exec, implicit $flat_scr :: (load store seq_cst 4, addrspace 1)
|
||||||
|
; GFX7-FLAT: $vgpr0 = COPY [[FLAT_ATOMIC_CMPSWAP_RTN]]
|
||||||
|
; GFX8-LABEL: name: amdgpu_atomic_cmpxchg_s32_global_gepm4
|
||||||
|
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3
|
||||||
|
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||||
|
; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||||
|
; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
|
||||||
|
; GFX8: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1
|
||||||
|
; GFX8: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294967292, implicit $exec
|
||||||
|
; GFX8: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
|
||||||
|
; GFX8: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1
|
||||||
|
; GFX8: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
|
||||||
|
; GFX8: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0
|
||||||
|
; GFX8: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
|
||||||
|
; GFX8: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1
|
||||||
|
; GFX8: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY3]], [[COPY4]], 0, implicit $exec
|
||||||
|
; GFX8: %12:vgpr_32, dead %14:sreg_64_xexec = V_ADDC_U32_e64 [[COPY5]], [[COPY6]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec
|
||||||
|
; GFX8: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %12, %subreg.sub1
|
||||||
|
; GFX8: [[FLAT_ATOMIC_CMPSWAP_RTN:%[0-9]+]]:vgpr_32 = FLAT_ATOMIC_CMPSWAP_RTN [[REG_SEQUENCE2]], [[REG_SEQUENCE]], 0, 0, implicit $exec, implicit $flat_scr :: (load store seq_cst 4, addrspace 1)
|
||||||
|
; GFX8: $vgpr0 = COPY [[FLAT_ATOMIC_CMPSWAP_RTN]]
|
||||||
|
; GFX9-LABEL: name: amdgpu_atomic_cmpxchg_s32_global_gepm4
|
||||||
|
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3
|
||||||
|
; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||||
|
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||||
|
; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
|
||||||
|
; GFX9: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1
|
||||||
|
; GFX9: [[GLOBAL_ATOMIC_CMPSWAP_RTN:%[0-9]+]]:vgpr_32 = GLOBAL_ATOMIC_CMPSWAP_RTN [[COPY]], [[REG_SEQUENCE]], -4, 0, implicit $exec :: (load store seq_cst 4, addrspace 1)
|
||||||
|
; GFX9: $vgpr0 = COPY [[GLOBAL_ATOMIC_CMPSWAP_RTN]]
|
||||||
|
; GFX10-LABEL: name: amdgpu_atomic_cmpxchg_s32_global_gepm4
|
||||||
|
; GFX10: liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3
|
||||||
|
; GFX10: $vcc_hi = IMPLICIT_DEF
|
||||||
|
; GFX10: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||||
|
; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||||
|
; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
|
||||||
|
; GFX10: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1
|
||||||
|
; GFX10: [[GLOBAL_ATOMIC_CMPSWAP_RTN:%[0-9]+]]:vgpr_32 = GLOBAL_ATOMIC_CMPSWAP_RTN [[COPY]], [[REG_SEQUENCE]], -4, 0, implicit $exec :: (load store seq_cst 4, addrspace 1)
|
||||||
|
; GFX10: $vgpr0 = COPY [[GLOBAL_ATOMIC_CMPSWAP_RTN]]
|
||||||
|
%0:vgpr(p1) = COPY $vgpr0_vgpr1
|
||||||
|
%1:vgpr(s32) = COPY $vgpr2
|
||||||
|
%2:vgpr(s32) = COPY $vgpr3
|
||||||
|
%3:vgpr(<2 x s32>) = G_BUILD_VECTOR %1, %2
|
||||||
|
%4:vgpr(s64) = G_CONSTANT i64 -4
|
||||||
|
%5:vgpr(p1) = G_PTR_ADD %0, %4
|
||||||
|
%6:vgpr(s32) = G_AMDGPU_ATOMIC_CMPXCHG %5, %3 :: (load store seq_cst 4, addrspace 1)
|
||||||
|
$vgpr0 = COPY %6
|
||||||
|
|
||||||
|
...
|
||||||
|
|
||||||
|
---
|
||||||
|
name: amdgpu_atomic_cmpxchg_s32_global_nortn
|
||||||
|
legalized: true
|
||||||
|
regBankSelected: true
|
||||||
|
tracksRegLiveness: true
|
||||||
|
body: |
|
||||||
|
bb.0:
|
||||||
|
liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3
|
||||||
|
|
||||||
|
; GFX6-LABEL: name: amdgpu_atomic_cmpxchg_s32_global_nortn
|
||||||
|
; GFX6: liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3
|
||||||
|
; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||||
|
; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||||
|
; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
|
||||||
|
; GFX6: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1
|
||||||
|
; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
|
||||||
|
; GFX6: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440
|
||||||
|
; GFX6: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
|
||||||
|
; GFX6: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
|
||||||
|
; GFX6: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3
|
||||||
|
; GFX6: [[BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN [[REG_SEQUENCE]], [[COPY]], [[REG_SEQUENCE2]], 0, 0, 0, implicit $exec :: (load store seq_cst 4, addrspace 1)
|
||||||
|
; GFX6: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN]].sub0
|
||||||
|
; GFX7-LABEL: name: amdgpu_atomic_cmpxchg_s32_global_nortn
|
||||||
|
; GFX7: liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3
|
||||||
|
; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||||
|
; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||||
|
; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
|
||||||
|
; GFX7: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1
|
||||||
|
; GFX7: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
|
||||||
|
; GFX7: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440
|
||||||
|
; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
|
||||||
|
; GFX7: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
|
||||||
|
; GFX7: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3
|
||||||
|
; GFX7: [[BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN [[REG_SEQUENCE]], [[COPY]], [[REG_SEQUENCE2]], 0, 0, 0, implicit $exec :: (load store seq_cst 4, addrspace 1)
|
||||||
|
; GFX7: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN]].sub0
|
||||||
|
; GFX7-FLAT-LABEL: name: amdgpu_atomic_cmpxchg_s32_global_nortn
|
||||||
|
; GFX7-FLAT: liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3
|
||||||
|
; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||||
|
; GFX7-FLAT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||||
|
; GFX7-FLAT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
|
||||||
|
; GFX7-FLAT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1
|
||||||
|
; GFX7-FLAT: [[FLAT_ATOMIC_CMPSWAP_RTN:%[0-9]+]]:vgpr_32 = FLAT_ATOMIC_CMPSWAP_RTN [[COPY]], [[REG_SEQUENCE]], 0, 0, implicit $exec, implicit $flat_scr :: (load store seq_cst 4, addrspace 1)
|
||||||
|
; GFX8-LABEL: name: amdgpu_atomic_cmpxchg_s32_global_nortn
|
||||||
|
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3
|
||||||
|
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||||
|
; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||||
|
; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
|
||||||
|
; GFX8: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1
|
||||||
|
; GFX8: [[FLAT_ATOMIC_CMPSWAP_RTN:%[0-9]+]]:vgpr_32 = FLAT_ATOMIC_CMPSWAP_RTN [[COPY]], [[REG_SEQUENCE]], 0, 0, implicit $exec, implicit $flat_scr :: (load store seq_cst 4, addrspace 1)
|
||||||
|
; GFX9-LABEL: name: amdgpu_atomic_cmpxchg_s32_global_nortn
|
||||||
|
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3
|
||||||
|
; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||||
|
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||||
|
; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
|
||||||
|
; GFX9: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1
|
||||||
|
; GFX9: [[GLOBAL_ATOMIC_CMPSWAP_RTN:%[0-9]+]]:vgpr_32 = GLOBAL_ATOMIC_CMPSWAP_RTN [[COPY]], [[REG_SEQUENCE]], 0, 0, implicit $exec :: (load store seq_cst 4, addrspace 1)
|
||||||
|
; GFX10-LABEL: name: amdgpu_atomic_cmpxchg_s32_global_nortn
|
||||||
|
; GFX10: liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3
|
||||||
|
; GFX10: $vcc_hi = IMPLICIT_DEF
|
||||||
|
; GFX10: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||||
|
; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||||
|
; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
|
||||||
|
; GFX10: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1
|
||||||
|
; GFX10: [[GLOBAL_ATOMIC_CMPSWAP_RTN:%[0-9]+]]:vgpr_32 = GLOBAL_ATOMIC_CMPSWAP_RTN [[COPY]], [[REG_SEQUENCE]], 0, 0, implicit $exec :: (load store seq_cst 4, addrspace 1)
|
||||||
|
%0:vgpr(p1) = COPY $vgpr0_vgpr1
|
||||||
|
%1:vgpr(s32) = COPY $vgpr2
|
||||||
|
%2:vgpr(s32) = COPY $vgpr3
|
||||||
|
%3:vgpr(<2 x s32>) = G_BUILD_VECTOR %1, %2
|
||||||
|
%4:vgpr(s32) = G_AMDGPU_ATOMIC_CMPXCHG %0, %3 :: (load store seq_cst 4, addrspace 1)
|
||||||
|
|
||||||
|
...
|
||||||
|
|
||||||
|
---
|
||||||
|
name: amdgpu_atomic_cmpxchg_s64_global_nortn
|
||||||
|
legalized: true
|
||||||
|
regBankSelected: true
|
||||||
|
tracksRegLiveness: true
|
||||||
|
body: |
|
||||||
|
bb.0:
|
||||||
|
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
|
||||||
|
|
||||||
|
; GFX6-LABEL: name: amdgpu_atomic_cmpxchg_s64_global_nortn
|
||||||
|
; GFX6: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
|
||||||
|
; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||||
|
; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||||
|
; GFX6: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr4_vgpr5
|
||||||
|
; GFX6: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0_sub1, [[COPY2]], %subreg.sub2_sub3
|
||||||
|
; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
|
||||||
|
; GFX6: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440
|
||||||
|
; GFX6: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
|
||||||
|
; GFX6: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
|
||||||
|
; GFX6: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3
|
||||||
|
; GFX6: [[BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN [[REG_SEQUENCE]], [[COPY]], [[REG_SEQUENCE2]], 0, 0, 0, implicit $exec :: (load store seq_cst 8, addrspace 1)
|
||||||
|
; GFX6: [[COPY3:%[0-9]+]]:vreg_64 = COPY killed [[BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN]].sub0_sub1
|
||||||
|
; GFX7-LABEL: name: amdgpu_atomic_cmpxchg_s64_global_nortn
|
||||||
|
; GFX7: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
|
||||||
|
; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||||
|
; GFX7: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||||
|
; GFX7: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr4_vgpr5
|
||||||
|
; GFX7: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0_sub1, [[COPY2]], %subreg.sub2_sub3
|
||||||
|
; GFX7: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
|
||||||
|
; GFX7: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440
|
||||||
|
; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
|
||||||
|
; GFX7: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
|
||||||
|
; GFX7: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3
|
||||||
|
; GFX7: [[BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN [[REG_SEQUENCE]], [[COPY]], [[REG_SEQUENCE2]], 0, 0, 0, implicit $exec :: (load store seq_cst 8, addrspace 1)
|
||||||
|
; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY killed [[BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN]].sub0_sub1
|
||||||
|
; GFX7-FLAT-LABEL: name: amdgpu_atomic_cmpxchg_s64_global_nortn
|
||||||
|
; GFX7-FLAT: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
|
||||||
|
; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||||
|
; GFX7-FLAT: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||||
|
; GFX7-FLAT: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr4_vgpr5
|
||||||
|
; GFX7-FLAT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0_sub1, [[COPY2]], %subreg.sub2_sub3
|
||||||
|
; GFX7-FLAT: [[FLAT_ATOMIC_CMPSWAP_X2_RTN:%[0-9]+]]:vreg_64 = FLAT_ATOMIC_CMPSWAP_X2_RTN [[COPY]], [[REG_SEQUENCE]], 0, 0, implicit $exec, implicit $flat_scr :: (load store seq_cst 8, addrspace 1)
|
||||||
|
; GFX8-LABEL: name: amdgpu_atomic_cmpxchg_s64_global_nortn
|
||||||
|
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
|
||||||
|
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||||
|
; GFX8: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||||
|
; GFX8: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr4_vgpr5
|
||||||
|
; GFX8: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0_sub1, [[COPY2]], %subreg.sub2_sub3
|
||||||
|
; GFX8: [[FLAT_ATOMIC_CMPSWAP_X2_RTN:%[0-9]+]]:vreg_64 = FLAT_ATOMIC_CMPSWAP_X2_RTN [[COPY]], [[REG_SEQUENCE]], 0, 0, implicit $exec, implicit $flat_scr :: (load store seq_cst 8, addrspace 1)
|
||||||
|
; GFX9-LABEL: name: amdgpu_atomic_cmpxchg_s64_global_nortn
|
||||||
|
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
|
||||||
|
; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||||
|
; GFX9: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||||
|
; GFX9: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr4_vgpr5
|
||||||
|
; GFX9: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0_sub1, [[COPY2]], %subreg.sub2_sub3
|
||||||
|
; GFX9: [[GLOBAL_ATOMIC_CMPSWAP_X2_RTN:%[0-9]+]]:vreg_64 = GLOBAL_ATOMIC_CMPSWAP_X2_RTN [[COPY]], [[REG_SEQUENCE]], 0, 0, implicit $exec :: (load store seq_cst 8, addrspace 1)
|
||||||
|
; GFX10-LABEL: name: amdgpu_atomic_cmpxchg_s64_global_nortn
|
||||||
|
; GFX10: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
|
||||||
|
; GFX10: $vcc_hi = IMPLICIT_DEF
|
||||||
|
; GFX10: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||||
|
; GFX10: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||||
|
; GFX10: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr4_vgpr5
|
||||||
|
; GFX10: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0_sub1, [[COPY2]], %subreg.sub2_sub3
|
||||||
|
; GFX10: [[GLOBAL_ATOMIC_CMPSWAP_X2_RTN:%[0-9]+]]:vreg_64 = GLOBAL_ATOMIC_CMPSWAP_X2_RTN [[COPY]], [[REG_SEQUENCE]], 0, 0, implicit $exec :: (load store seq_cst 8, addrspace 1)
|
||||||
|
%0:vgpr(p1) = COPY $vgpr0_vgpr1
|
||||||
|
%1:vgpr(s64) = COPY $vgpr2_vgpr3
|
||||||
|
%2:vgpr(s64) = COPY $vgpr4_vgpr5
|
||||||
|
%3:vgpr(<2 x s64>) = G_BUILD_VECTOR %1, %2
|
||||||
|
%4:vgpr(s64) = G_AMDGPU_ATOMIC_CMPXCHG %0, %3 :: (load store seq_cst 8, addrspace 1)
|
||||||
|
|
||||||
|
...
|
||||||
|
|
||||||
|
---
|
||||||
|
name: amdgpu_atomic_cmpxchg_s32_global_sgpr_ptr
|
||||||
|
legalized: true
|
||||||
|
regBankSelected: true
|
||||||
|
tracksRegLiveness: true
|
||||||
|
body: |
|
||||||
|
bb.0:
|
||||||
|
liveins: $sgpr0_sgpr1, $vgpr2, $vgpr3
|
||||||
|
|
||||||
|
; GFX6-LABEL: name: amdgpu_atomic_cmpxchg_s32_global_sgpr_ptr
|
||||||
|
; GFX6: liveins: $sgpr0_sgpr1, $vgpr2, $vgpr3
|
||||||
|
; GFX6: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
|
||||||
|
; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||||
|
; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
|
||||||
|
; GFX6: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1
|
||||||
|
; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967295
|
||||||
|
; GFX6: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440
|
||||||
|
; GFX6: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
|
||||||
|
; GFX6: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3
|
||||||
|
; GFX6: [[BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN [[REG_SEQUENCE]], [[REG_SEQUENCE2]], 0, 0, 0, implicit $exec :: (load store seq_cst 4, addrspace 1)
|
||||||
|
; GFX6: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN]].sub0
|
||||||
|
; GFX6: $vgpr0 = COPY [[COPY3]]
|
||||||
|
; GFX7-LABEL: name: amdgpu_atomic_cmpxchg_s32_global_sgpr_ptr
|
||||||
|
; GFX7: liveins: $sgpr0_sgpr1, $vgpr2, $vgpr3
|
||||||
|
; GFX7: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
|
||||||
|
; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||||
|
; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
|
||||||
|
; GFX7: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1
|
||||||
|
; GFX7: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967295
|
||||||
|
; GFX7: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440
|
||||||
|
; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
|
||||||
|
; GFX7: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3
|
||||||
|
; GFX7: [[BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN [[REG_SEQUENCE]], [[REG_SEQUENCE2]], 0, 0, 0, implicit $exec :: (load store seq_cst 4, addrspace 1)
|
||||||
|
; GFX7: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN]].sub0
|
||||||
|
; GFX7: $vgpr0 = COPY [[COPY3]]
|
||||||
|
; GFX7-FLAT-LABEL: name: amdgpu_atomic_cmpxchg_s32_global_sgpr_ptr
|
||||||
|
; GFX7-FLAT: liveins: $sgpr0_sgpr1, $vgpr2, $vgpr3
|
||||||
|
; GFX7-FLAT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
|
||||||
|
; GFX7-FLAT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||||
|
; GFX7-FLAT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
|
||||||
|
; GFX7-FLAT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1
|
||||||
|
; GFX7-FLAT: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[COPY]]
|
||||||
|
; GFX7-FLAT: [[FLAT_ATOMIC_CMPSWAP_RTN:%[0-9]+]]:vgpr_32 = FLAT_ATOMIC_CMPSWAP_RTN [[COPY3]], [[REG_SEQUENCE]], 0, 0, implicit $exec, implicit $flat_scr :: (load store seq_cst 4, addrspace 1)
|
||||||
|
; GFX7-FLAT: $vgpr0 = COPY [[FLAT_ATOMIC_CMPSWAP_RTN]]
|
||||||
|
; GFX8-LABEL: name: amdgpu_atomic_cmpxchg_s32_global_sgpr_ptr
|
||||||
|
; GFX8: liveins: $sgpr0_sgpr1, $vgpr2, $vgpr3
|
||||||
|
; GFX8: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
|
||||||
|
; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||||
|
; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
|
||||||
|
; GFX8: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1
|
||||||
|
; GFX8: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[COPY]]
|
||||||
|
; GFX8: [[FLAT_ATOMIC_CMPSWAP_RTN:%[0-9]+]]:vgpr_32 = FLAT_ATOMIC_CMPSWAP_RTN [[COPY3]], [[REG_SEQUENCE]], 0, 0, implicit $exec, implicit $flat_scr :: (load store seq_cst 4, addrspace 1)
|
||||||
|
; GFX8: $vgpr0 = COPY [[FLAT_ATOMIC_CMPSWAP_RTN]]
|
||||||
|
; GFX9-LABEL: name: amdgpu_atomic_cmpxchg_s32_global_sgpr_ptr
|
||||||
|
; GFX9: liveins: $sgpr0_sgpr1, $vgpr2, $vgpr3
|
||||||
|
; GFX9: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
|
||||||
|
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||||
|
; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
|
||||||
|
; GFX9: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1
|
||||||
|
; GFX9: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[COPY]]
|
||||||
|
; GFX9: [[GLOBAL_ATOMIC_CMPSWAP_RTN:%[0-9]+]]:vgpr_32 = GLOBAL_ATOMIC_CMPSWAP_RTN [[COPY3]], [[REG_SEQUENCE]], 0, 0, implicit $exec :: (load store seq_cst 4, addrspace 1)
|
||||||
|
; GFX9: $vgpr0 = COPY [[GLOBAL_ATOMIC_CMPSWAP_RTN]]
|
||||||
|
; GFX10-LABEL: name: amdgpu_atomic_cmpxchg_s32_global_sgpr_ptr
|
||||||
|
; GFX10: liveins: $sgpr0_sgpr1, $vgpr2, $vgpr3
|
||||||
|
; GFX10: $vcc_hi = IMPLICIT_DEF
|
||||||
|
; GFX10: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
|
||||||
|
; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||||
|
; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
|
||||||
|
; GFX10: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1
|
||||||
|
; GFX10: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[COPY]]
|
||||||
|
; GFX10: [[GLOBAL_ATOMIC_CMPSWAP_RTN:%[0-9]+]]:vgpr_32 = GLOBAL_ATOMIC_CMPSWAP_RTN [[COPY3]], [[REG_SEQUENCE]], 0, 0, implicit $exec :: (load store seq_cst 4, addrspace 1)
|
||||||
|
; GFX10: $vgpr0 = COPY [[GLOBAL_ATOMIC_CMPSWAP_RTN]]
|
||||||
|
%0:sgpr(p1) = COPY $sgpr0_sgpr1
|
||||||
|
%1:vgpr(s32) = COPY $vgpr2
|
||||||
|
%2:vgpr(s32) = COPY $vgpr3
|
||||||
|
%3:vgpr(<2 x s32>) = G_BUILD_VECTOR %1, %2
|
||||||
|
%4:vgpr(s32) = G_AMDGPU_ATOMIC_CMPXCHG %0, %3 :: (load store seq_cst 4, addrspace 1)
|
||||||
|
$vgpr0 = COPY %4
|
||||||
|
|
||||||
|
...
|
||||||
|
|
||||||
|
---
|
||||||
|
name: amdgpu_atomic_cmpxchg_s32_global_sgpr_ptr_offset_4095
|
||||||
|
legalized: true
|
||||||
|
regBankSelected: true
|
||||||
|
tracksRegLiveness: true
|
||||||
|
body: |
|
||||||
|
bb.0:
|
||||||
|
liveins: $sgpr0_sgpr1, $vgpr2, $vgpr3
|
||||||
|
|
||||||
|
; GFX6-LABEL: name: amdgpu_atomic_cmpxchg_s32_global_sgpr_ptr_offset_4095
|
||||||
|
; GFX6: liveins: $sgpr0_sgpr1, $vgpr2, $vgpr3
|
||||||
|
; GFX6: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
|
||||||
|
; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||||
|
; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
|
||||||
|
; GFX6: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1
|
||||||
|
; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967295
|
||||||
|
; GFX6: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440
|
||||||
|
; GFX6: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
|
||||||
|
; GFX6: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3
|
||||||
|
; GFX6: [[BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN [[REG_SEQUENCE]], [[REG_SEQUENCE2]], 0, 4095, 0, implicit $exec :: (load store seq_cst 4, addrspace 1)
|
||||||
|
; GFX6: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN]].sub0
|
||||||
|
; GFX6: $vgpr0 = COPY [[COPY3]]
|
||||||
|
; GFX7-LABEL: name: amdgpu_atomic_cmpxchg_s32_global_sgpr_ptr_offset_4095
|
||||||
|
; GFX7: liveins: $sgpr0_sgpr1, $vgpr2, $vgpr3
|
||||||
|
; GFX7: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
|
||||||
|
; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||||
|
; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
|
||||||
|
; GFX7: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1
|
||||||
|
; GFX7: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967295
|
||||||
|
; GFX7: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440
|
||||||
|
; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
|
||||||
|
; GFX7: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3
|
||||||
|
; GFX7: [[BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN [[REG_SEQUENCE]], [[REG_SEQUENCE2]], 0, 4095, 0, implicit $exec :: (load store seq_cst 4, addrspace 1)
|
||||||
|
; GFX7: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN]].sub0
|
||||||
|
; GFX7: $vgpr0 = COPY [[COPY3]]
|
||||||
|
; GFX7-FLAT-LABEL: name: amdgpu_atomic_cmpxchg_s32_global_sgpr_ptr_offset_4095
|
||||||
|
; GFX7-FLAT: liveins: $sgpr0_sgpr1, $vgpr2, $vgpr3
|
||||||
|
; GFX7-FLAT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
|
||||||
|
; GFX7-FLAT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||||
|
; GFX7-FLAT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
|
||||||
|
; GFX7-FLAT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095
|
||||||
|
; GFX7-FLAT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
|
||||||
|
; GFX7-FLAT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
|
||||||
|
; GFX7-FLAT: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
|
||||||
|
; GFX7-FLAT: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE]].sub0
|
||||||
|
; GFX7-FLAT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
|
||||||
|
; GFX7-FLAT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE]].sub1
|
||||||
|
; GFX7-FLAT: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY3]], [[COPY4]], implicit-def $scc
|
||||||
|
; GFX7-FLAT: [[S_ADDC_U32_:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[COPY5]], [[COPY6]], implicit-def $scc, implicit $scc
|
||||||
|
; GFX7-FLAT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[S_ADD_U32_]], %subreg.sub0, [[S_ADDC_U32_]], %subreg.sub1
|
||||||
|
; GFX7-FLAT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1
|
||||||
|
; GFX7-FLAT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]]
|
||||||
|
; GFX7-FLAT: [[FLAT_ATOMIC_CMPSWAP_RTN:%[0-9]+]]:vgpr_32 = FLAT_ATOMIC_CMPSWAP_RTN [[COPY7]], [[REG_SEQUENCE2]], 0, 0, implicit $exec, implicit $flat_scr :: (load store seq_cst 4, addrspace 1)
|
||||||
|
; GFX7-FLAT: $vgpr0 = COPY [[FLAT_ATOMIC_CMPSWAP_RTN]]
|
||||||
|
; GFX8-LABEL: name: amdgpu_atomic_cmpxchg_s32_global_sgpr_ptr_offset_4095
|
||||||
|
; GFX8: liveins: $sgpr0_sgpr1, $vgpr2, $vgpr3
|
||||||
|
; GFX8: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
|
||||||
|
; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||||
|
; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
|
||||||
|
; GFX8: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095
|
||||||
|
; GFX8: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
|
||||||
|
; GFX8: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
|
||||||
|
; GFX8: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
|
||||||
|
; GFX8: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE]].sub0
|
||||||
|
; GFX8: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
|
||||||
|
; GFX8: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE]].sub1
|
||||||
|
; GFX8: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY3]], [[COPY4]], implicit-def $scc
|
||||||
|
; GFX8: [[S_ADDC_U32_:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[COPY5]], [[COPY6]], implicit-def $scc, implicit $scc
|
||||||
|
; GFX8: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[S_ADD_U32_]], %subreg.sub0, [[S_ADDC_U32_]], %subreg.sub1
|
||||||
|
; GFX8: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1
|
||||||
|
; GFX8: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]]
|
||||||
|
; GFX8: [[FLAT_ATOMIC_CMPSWAP_RTN:%[0-9]+]]:vgpr_32 = FLAT_ATOMIC_CMPSWAP_RTN [[COPY7]], [[REG_SEQUENCE2]], 0, 0, implicit $exec, implicit $flat_scr :: (load store seq_cst 4, addrspace 1)
|
||||||
|
; GFX8: $vgpr0 = COPY [[FLAT_ATOMIC_CMPSWAP_RTN]]
|
||||||
|
; GFX9-LABEL: name: amdgpu_atomic_cmpxchg_s32_global_sgpr_ptr_offset_4095
|
||||||
|
; GFX9: liveins: $sgpr0_sgpr1, $vgpr2, $vgpr3
|
||||||
|
; GFX9: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
|
||||||
|
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||||
|
; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
|
||||||
|
; GFX9: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1
|
||||||
|
; GFX9: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[COPY]]
|
||||||
|
; GFX9: [[GLOBAL_ATOMIC_CMPSWAP_RTN:%[0-9]+]]:vgpr_32 = GLOBAL_ATOMIC_CMPSWAP_RTN [[COPY3]], [[REG_SEQUENCE]], 4095, 0, implicit $exec :: (load store seq_cst 4, addrspace 1)
|
||||||
|
; GFX9: $vgpr0 = COPY [[GLOBAL_ATOMIC_CMPSWAP_RTN]]
|
||||||
|
; GFX10-LABEL: name: amdgpu_atomic_cmpxchg_s32_global_sgpr_ptr_offset_4095
|
||||||
|
; GFX10: liveins: $sgpr0_sgpr1, $vgpr2, $vgpr3
|
||||||
|
; GFX10: $vcc_hi = IMPLICIT_DEF
|
||||||
|
; GFX10: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
|
||||||
|
; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||||
|
; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
|
||||||
|
; GFX10: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095
|
||||||
|
; GFX10: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
|
||||||
|
; GFX10: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
|
||||||
|
; GFX10: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
|
||||||
|
; GFX10: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE]].sub0
|
||||||
|
; GFX10: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
|
||||||
|
; GFX10: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE]].sub1
|
||||||
|
; GFX10: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY3]], [[COPY4]], implicit-def $scc
|
||||||
|
; GFX10: [[S_ADDC_U32_:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[COPY5]], [[COPY6]], implicit-def $scc, implicit $scc
|
||||||
|
; GFX10: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[S_ADD_U32_]], %subreg.sub0, [[S_ADDC_U32_]], %subreg.sub1
|
||||||
|
; GFX10: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1
|
||||||
|
; GFX10: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]]
|
||||||
|
; GFX10: [[GLOBAL_ATOMIC_CMPSWAP_RTN:%[0-9]+]]:vgpr_32 = GLOBAL_ATOMIC_CMPSWAP_RTN [[COPY7]], [[REG_SEQUENCE2]], 0, 0, implicit $exec :: (load store seq_cst 4, addrspace 1)
|
||||||
|
; GFX10: $vgpr0 = COPY [[GLOBAL_ATOMIC_CMPSWAP_RTN]]
|
||||||
|
%0:sgpr(p1) = COPY $sgpr0_sgpr1
|
||||||
|
%1:vgpr(s32) = COPY $vgpr2
|
||||||
|
%2:vgpr(s32) = COPY $vgpr3
|
||||||
|
%3:sgpr(s64) = G_CONSTANT i64 4095
|
||||||
|
%4:sgpr(p1) = G_PTR_ADD %0, %3
|
||||||
|
%5:vgpr(<2 x s32>) = G_BUILD_VECTOR %1, %2
|
||||||
|
%6:vgpr(s32) = G_AMDGPU_ATOMIC_CMPXCHG %4, %5 :: (load store seq_cst 4, addrspace 1)
|
||||||
|
$vgpr0 = COPY %6
|
||||||
|
|
||||||
|
...
|
||||||
@ -1099,3 +1099,197 @@ define amdgpu_ps float @mubuf_atomicrmw_sgpr_ptr_vgpr_offset(i32 addrspace(1)* i
|
|||||||
%cast = bitcast i32 %result to float
|
%cast = bitcast i32 %result to float
|
||||||
ret float %cast
|
ret float %cast
|
||||||
}
|
}
|
||||||
|
|
||||||
|
define amdgpu_ps float @mubuf_cmpxchg_sgpr_ptr_offset4095(i32 addrspace(1)* inreg %ptr, i32 %old, i32 %in) {
|
||||||
|
; GFX6-LABEL: mubuf_cmpxchg_sgpr_ptr_offset4095:
|
||||||
|
; GFX6: ; %bb.0:
|
||||||
|
; GFX6-NEXT: s_mov_b32 s0, s2
|
||||||
|
; GFX6-NEXT: s_mov_b32 s1, s3
|
||||||
|
; GFX6-NEXT: v_mov_b32_e32 v2, v0
|
||||||
|
; GFX6-NEXT: s_mov_b32 s2, -1
|
||||||
|
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
||||||
|
; GFX6-NEXT: s_movk_i32 s4, 0x3ffc
|
||||||
|
; GFX6-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
||||||
|
; GFX6-NEXT: buffer_atomic_cmpswap v[1:2], off, s[0:3], s4 glc
|
||||||
|
; GFX6-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
||||||
|
; GFX6-NEXT: buffer_wbinvl1
|
||||||
|
; GFX6-NEXT: v_mov_b32_e32 v0, v1
|
||||||
|
; GFX6-NEXT: s_waitcnt expcnt(0)
|
||||||
|
; GFX6-NEXT: ; return to shader part epilog
|
||||||
|
;
|
||||||
|
; GFX7-LABEL: mubuf_cmpxchg_sgpr_ptr_offset4095:
|
||||||
|
; GFX7: ; %bb.0:
|
||||||
|
; GFX7-NEXT: s_mov_b32 s0, s2
|
||||||
|
; GFX7-NEXT: s_mov_b32 s1, s3
|
||||||
|
; GFX7-NEXT: v_mov_b32_e32 v2, v0
|
||||||
|
; GFX7-NEXT: s_mov_b32 s2, -1
|
||||||
|
; GFX7-NEXT: s_mov_b32 s3, 0xf000
|
||||||
|
; GFX7-NEXT: s_movk_i32 s4, 0x3ffc
|
||||||
|
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
||||||
|
; GFX7-NEXT: buffer_atomic_cmpswap v[1:2], off, s[0:3], s4 glc
|
||||||
|
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
||||||
|
; GFX7-NEXT: buffer_wbinvl1
|
||||||
|
; GFX7-NEXT: v_mov_b32_e32 v0, v1
|
||||||
|
; GFX7-NEXT: ; return to shader part epilog
|
||||||
|
%gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4095
|
||||||
|
%result.struct = cmpxchg i32 addrspace(1)* %gep, i32 %old, i32 %in seq_cst seq_cst
|
||||||
|
%result = extractvalue { i32, i1 } %result.struct, 0
|
||||||
|
%cast = bitcast i32 %result to float
|
||||||
|
ret float %cast
|
||||||
|
}
|
||||||
|
|
||||||
|
define amdgpu_ps float @mubuf_cmpxchg_sgpr_ptr_offset4294967296(i32 addrspace(1)* inreg %ptr, i32 %old, i32 %in) {
|
||||||
|
; GFX6-LABEL: mubuf_cmpxchg_sgpr_ptr_offset4294967296:
|
||||||
|
; GFX6: ; %bb.0:
|
||||||
|
; GFX6-NEXT: s_mov_b32 s4, 0
|
||||||
|
; GFX6-NEXT: s_mov_b32 s5, 4
|
||||||
|
; GFX6-NEXT: v_mov_b32_e32 v3, s4
|
||||||
|
; GFX6-NEXT: s_mov_b32 s0, s2
|
||||||
|
; GFX6-NEXT: s_mov_b32 s1, s3
|
||||||
|
; GFX6-NEXT: v_mov_b32_e32 v2, v0
|
||||||
|
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
||||||
|
; GFX6-NEXT: s_mov_b32 s2, s4
|
||||||
|
; GFX6-NEXT: v_mov_b32_e32 v4, s5
|
||||||
|
; GFX6-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
||||||
|
; GFX6-NEXT: buffer_atomic_cmpswap v[1:2], v[3:4], s[0:3], 0 addr64 glc
|
||||||
|
; GFX6-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
||||||
|
; GFX6-NEXT: buffer_wbinvl1
|
||||||
|
; GFX6-NEXT: v_mov_b32_e32 v0, v1
|
||||||
|
; GFX6-NEXT: s_waitcnt expcnt(0)
|
||||||
|
; GFX6-NEXT: ; return to shader part epilog
|
||||||
|
;
|
||||||
|
; GFX7-LABEL: mubuf_cmpxchg_sgpr_ptr_offset4294967296:
|
||||||
|
; GFX7: ; %bb.0:
|
||||||
|
; GFX7-NEXT: s_mov_b32 s4, 0
|
||||||
|
; GFX7-NEXT: s_mov_b32 s5, 4
|
||||||
|
; GFX7-NEXT: v_mov_b32_e32 v3, s4
|
||||||
|
; GFX7-NEXT: s_mov_b32 s0, s2
|
||||||
|
; GFX7-NEXT: s_mov_b32 s1, s3
|
||||||
|
; GFX7-NEXT: v_mov_b32_e32 v2, v0
|
||||||
|
; GFX7-NEXT: s_mov_b32 s3, 0xf000
|
||||||
|
; GFX7-NEXT: s_mov_b32 s2, s4
|
||||||
|
; GFX7-NEXT: v_mov_b32_e32 v4, s5
|
||||||
|
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
||||||
|
; GFX7-NEXT: buffer_atomic_cmpswap v[1:2], v[3:4], s[0:3], 0 addr64 glc
|
||||||
|
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
||||||
|
; GFX7-NEXT: buffer_wbinvl1
|
||||||
|
; GFX7-NEXT: v_mov_b32_e32 v0, v1
|
||||||
|
; GFX7-NEXT: ; return to shader part epilog
|
||||||
|
%gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4294967296
|
||||||
|
%result.struct = cmpxchg i32 addrspace(1)* %gep, i32 %old, i32 %in seq_cst seq_cst
|
||||||
|
%result = extractvalue { i32, i1 } %result.struct, 0
|
||||||
|
%cast = bitcast i32 %result to float
|
||||||
|
ret float %cast
|
||||||
|
}
|
||||||
|
|
||||||
|
define amdgpu_ps float @mubuf_cmpxchg_vgpr_ptr_offset4095(i32 addrspace(1)* %ptr, i32 %old, i32 %in) {
|
||||||
|
; GFX6-LABEL: mubuf_cmpxchg_vgpr_ptr_offset4095:
|
||||||
|
; GFX6: ; %bb.0:
|
||||||
|
; GFX6-NEXT: v_mov_b32_e32 v4, v2
|
||||||
|
; GFX6-NEXT: s_mov_b32 s2, 0
|
||||||
|
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
||||||
|
; GFX6-NEXT: s_mov_b64 s[0:1], 0
|
||||||
|
; GFX6-NEXT: s_movk_i32 s4, 0x3ffc
|
||||||
|
; GFX6-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
||||||
|
; GFX6-NEXT: buffer_atomic_cmpswap v[3:4], v[0:1], s[0:3], s4 addr64 glc
|
||||||
|
; GFX6-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
||||||
|
; GFX6-NEXT: buffer_wbinvl1
|
||||||
|
; GFX6-NEXT: v_mov_b32_e32 v0, v3
|
||||||
|
; GFX6-NEXT: s_waitcnt expcnt(0)
|
||||||
|
; GFX6-NEXT: ; return to shader part epilog
|
||||||
|
;
|
||||||
|
; GFX7-LABEL: mubuf_cmpxchg_vgpr_ptr_offset4095:
|
||||||
|
; GFX7: ; %bb.0:
|
||||||
|
; GFX7-NEXT: v_mov_b32_e32 v4, v2
|
||||||
|
; GFX7-NEXT: s_mov_b32 s2, 0
|
||||||
|
; GFX7-NEXT: s_mov_b32 s3, 0xf000
|
||||||
|
; GFX7-NEXT: s_mov_b64 s[0:1], 0
|
||||||
|
; GFX7-NEXT: s_movk_i32 s4, 0x3ffc
|
||||||
|
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
||||||
|
; GFX7-NEXT: buffer_atomic_cmpswap v[3:4], v[0:1], s[0:3], s4 addr64 glc
|
||||||
|
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
||||||
|
; GFX7-NEXT: buffer_wbinvl1
|
||||||
|
; GFX7-NEXT: v_mov_b32_e32 v0, v3
|
||||||
|
; GFX7-NEXT: ; return to shader part epilog
|
||||||
|
%gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4095
|
||||||
|
%result.struct = cmpxchg i32 addrspace(1)* %gep, i32 %old, i32 %in seq_cst seq_cst
|
||||||
|
%result = extractvalue { i32, i1 } %result.struct, 0
|
||||||
|
%cast = bitcast i32 %result to float
|
||||||
|
ret float %cast
|
||||||
|
}
|
||||||
|
|
||||||
|
define amdgpu_ps float @mubuf_cmpxchg_vgpr_ptr_offset4294967296(i32 addrspace(1)* %ptr, i32 %old, i32 %in) {
|
||||||
|
; GFX6-LABEL: mubuf_cmpxchg_vgpr_ptr_offset4294967296:
|
||||||
|
; GFX6: ; %bb.0:
|
||||||
|
; GFX6-NEXT: s_mov_b32 s0, 0
|
||||||
|
; GFX6-NEXT: v_mov_b32_e32 v4, v2
|
||||||
|
; GFX6-NEXT: s_mov_b32 s1, 4
|
||||||
|
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
||||||
|
; GFX6-NEXT: s_mov_b32 s2, s0
|
||||||
|
; GFX6-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
||||||
|
; GFX6-NEXT: buffer_atomic_cmpswap v[3:4], v[0:1], s[0:3], 0 addr64 glc
|
||||||
|
; GFX6-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
||||||
|
; GFX6-NEXT: buffer_wbinvl1
|
||||||
|
; GFX6-NEXT: v_mov_b32_e32 v0, v3
|
||||||
|
; GFX6-NEXT: s_waitcnt expcnt(0)
|
||||||
|
; GFX6-NEXT: ; return to shader part epilog
|
||||||
|
;
|
||||||
|
; GFX7-LABEL: mubuf_cmpxchg_vgpr_ptr_offset4294967296:
|
||||||
|
; GFX7: ; %bb.0:
|
||||||
|
; GFX7-NEXT: s_mov_b32 s0, 0
|
||||||
|
; GFX7-NEXT: v_mov_b32_e32 v4, v2
|
||||||
|
; GFX7-NEXT: s_mov_b32 s1, 4
|
||||||
|
; GFX7-NEXT: s_mov_b32 s3, 0xf000
|
||||||
|
; GFX7-NEXT: s_mov_b32 s2, s0
|
||||||
|
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
||||||
|
; GFX7-NEXT: buffer_atomic_cmpswap v[3:4], v[0:1], s[0:3], 0 addr64 glc
|
||||||
|
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
||||||
|
; GFX7-NEXT: buffer_wbinvl1
|
||||||
|
; GFX7-NEXT: v_mov_b32_e32 v0, v3
|
||||||
|
; GFX7-NEXT: ; return to shader part epilog
|
||||||
|
%gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4294967296
|
||||||
|
%result.struct = cmpxchg i32 addrspace(1)* %gep, i32 %old, i32 %in seq_cst seq_cst
|
||||||
|
%result = extractvalue { i32, i1 } %result.struct, 0
|
||||||
|
%cast = bitcast i32 %result to float
|
||||||
|
ret float %cast
|
||||||
|
}
|
||||||
|
|
||||||
|
define amdgpu_ps float @mubuf_cmpxchg_sgpr_ptr_vgpr_offset(i32 addrspace(1)* inreg %ptr, i32 %voffset, i32 %old, i32 %in) {
|
||||||
|
; GFX6-LABEL: mubuf_cmpxchg_sgpr_ptr_vgpr_offset:
|
||||||
|
; GFX6: ; %bb.0:
|
||||||
|
; GFX6-NEXT: v_mov_b32_e32 v3, v1
|
||||||
|
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v0
|
||||||
|
; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
|
||||||
|
; GFX6-NEXT: s_mov_b32 s0, s2
|
||||||
|
; GFX6-NEXT: s_mov_b32 s1, s3
|
||||||
|
; GFX6-NEXT: s_mov_b32 s2, 0
|
||||||
|
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
||||||
|
; GFX6-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
||||||
|
; GFX6-NEXT: buffer_atomic_cmpswap v[2:3], v[0:1], s[0:3], 0 addr64 glc
|
||||||
|
; GFX6-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
||||||
|
; GFX6-NEXT: buffer_wbinvl1
|
||||||
|
; GFX6-NEXT: v_mov_b32_e32 v0, v2
|
||||||
|
; GFX6-NEXT: s_waitcnt expcnt(0)
|
||||||
|
; GFX6-NEXT: ; return to shader part epilog
|
||||||
|
;
|
||||||
|
; GFX7-LABEL: mubuf_cmpxchg_sgpr_ptr_vgpr_offset:
|
||||||
|
; GFX7: ; %bb.0:
|
||||||
|
; GFX7-NEXT: v_mov_b32_e32 v3, v1
|
||||||
|
; GFX7-NEXT: v_ashrrev_i32_e32 v1, 31, v0
|
||||||
|
; GFX7-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
|
||||||
|
; GFX7-NEXT: s_mov_b32 s0, s2
|
||||||
|
; GFX7-NEXT: s_mov_b32 s1, s3
|
||||||
|
; GFX7-NEXT: s_mov_b32 s2, 0
|
||||||
|
; GFX7-NEXT: s_mov_b32 s3, 0xf000
|
||||||
|
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
||||||
|
; GFX7-NEXT: buffer_atomic_cmpswap v[2:3], v[0:1], s[0:3], 0 addr64 glc
|
||||||
|
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
||||||
|
; GFX7-NEXT: buffer_wbinvl1
|
||||||
|
; GFX7-NEXT: v_mov_b32_e32 v0, v2
|
||||||
|
; GFX7-NEXT: ; return to shader part epilog
|
||||||
|
%gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 %voffset
|
||||||
|
%result.struct = cmpxchg i32 addrspace(1)* %gep, i32 %old, i32 %in seq_cst seq_cst
|
||||||
|
%result = extractvalue { i32, i1 } %result.struct, 0
|
||||||
|
%cast = bitcast i32 %result to float
|
||||||
|
ret float %cast
|
||||||
|
}
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user