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[PowerPC] Add Itineraries for STWU/STWUX etc

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When doing some instruction scheduling work, we noticed some missing itineraries.

Before we switch to machine scheduler, those missing itineraries might not have impact to actually scheduling, 
because we can still get same latency due to default values.

With machine scheduler, however, itineraries will have impact to scheduling.
eg: NumMicroOps will default to be 0 if there is NO itineraries for specific instruction class.
And most of the instruction class with itineraries will have NumMicroOps default to 1.

This will has impact on the count of RetiredMOps, affects the Pending/Available Queue, 
then causing different scheduling or suboptimal scheduling further.

This patch is for STWU/STWUX (IIC_LdStStoreUpd ) for P8.

Since there are already multiple IIC for store update, this patch also merge
IIC_LdStSTDU/IIC_LdStStoreUpd to IIC_LdStSTU
IIC_LdStSTDUX to IIC_LdStSTUX

and we add a new testcase in https://reviews.llvm.org/D54699 to show the difference.

Differential Revision: https://reviews.llvm.org/D54700

llvm-svn: 347311
This commit is contained in:
Jinsong Ji 2018-11-20 15:11:42 +00:00
parent 22448a7d17
commit 9a4c805887
16 changed files with 52 additions and 56 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
lib/Target/PowerPC/PPCHazardRecognizers.cpp
View File

@ -103,7 +103,7 @@ bool PPCDispatchGroupSBHazardRecognizer::mustComeFirst(const MCInstrDesc *MCID,
case PPC::Sched::IIC_LdStLHA:
case PPC::Sched::IIC_LdStLHAU:
case PPC::Sched::IIC_LdStLWA:
case PPC::Sched::IIC_LdStSTDU:
case PPC::Sched::IIC_LdStSTU:
case PPC::Sched::IIC_LdStSTFDU:
NSlots = 2;
break;
@ -112,7 +112,7 @@ bool PPCDispatchGroupSBHazardRecognizer::mustComeFirst(const MCInstrDesc *MCID,
case PPC::Sched::IIC_LdStLHAUX:
case PPC::Sched::IIC_LdStLWARX:
case PPC::Sched::IIC_LdStLDARX:
case PPC::Sched::IIC_LdStSTDUX:
case PPC::Sched::IIC_LdStSTUX:
case PPC::Sched::IIC_LdStSTDCX:
case PPC::Sched::IIC_LdStSTWCX:
case PPC::Sched::IIC_BrMCRX: // mtcr

16
lib/Target/PowerPC/PPCInstr64Bit.td
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@ -1222,30 +1222,30 @@ def STDBRX: XForm_8_memOp<31, 660, (outs), (ins g8rc:$rS, memrr:$dst),
let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in {
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
"stbu $rS, $dst", IIC_LdStStoreUpd, []>,
"stbu $rS, $dst", IIC_LdStSTU, []>,
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
"sthu $rS, $dst", IIC_LdStStoreUpd, []>,
"sthu $rS, $dst", IIC_LdStSTU, []>,
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
"stwu $rS, $dst", IIC_LdStStoreUpd, []>,
"stwu $rS, $dst", IIC_LdStSTU, []>,
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
def STBUX8: XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res),
(ins g8rc:$rS, memrr:$dst),
"stbux $rS, $dst", IIC_LdStStoreUpd, []>,
"stbux $rS, $dst", IIC_LdStSTUX, []>,
RegConstraint<"$dst.ptrreg = $ea_res">,
NoEncode<"$ea_res">,
PPC970_DGroup_Cracked;
def STHUX8: XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res),
(ins g8rc:$rS, memrr:$dst),
"sthux $rS, $dst", IIC_LdStStoreUpd, []>,
"sthux $rS, $dst", IIC_LdStSTUX, []>,
RegConstraint<"$dst.ptrreg = $ea_res">,
NoEncode<"$ea_res">,
PPC970_DGroup_Cracked;
def STWUX8: XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res),
(ins g8rc:$rS, memrr:$dst),
"stwux $rS, $dst", IIC_LdStStoreUpd, []>,
"stwux $rS, $dst", IIC_LdStSTUX, []>,
RegConstraint<"$dst.ptrreg = $ea_res">,
NoEncode<"$ea_res">,
PPC970_DGroup_Cracked;
@ -1253,13 +1253,13 @@ def STWUX8: XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res),
def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res),
(ins g8rc:$rS, memrix:$dst),
"stdu $rS, $dst", IIC_LdStSTDU, []>,
"stdu $rS, $dst", IIC_LdStSTU, []>,
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">,
isPPC64;
def STDUX : XForm_8_memOp<31, 181, (outs ptr_rc_nor0:$ea_res),
(ins g8rc:$rS, memrr:$dst),
"stdux $rS, $dst", IIC_LdStSTDUX, []>,
"stdux $rS, $dst", IIC_LdStSTUX, []>,
RegConstraint<"$dst.ptrreg = $ea_res">,
NoEncode<"$ea_res">,
PPC970_DGroup_Cracked, isPPC64;

12
lib/Target/PowerPC/PPCInstrInfo.td
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@ -2016,13 +2016,13 @@ def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst),
// Unindexed (r+i) Stores with Update (preinc).
let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in {
def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
"stbu $rS, $dst", IIC_LdStStoreUpd, []>,
"stbu $rS, $dst", IIC_LdStSTU, []>,
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
"sthu $rS, $dst", IIC_LdStStoreUpd, []>,
"sthu $rS, $dst", IIC_LdStSTU, []>,
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
"stwu $rS, $dst", IIC_LdStStoreUpd, []>,
"stwu $rS, $dst", IIC_LdStSTU, []>,
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
let Predicates = [HasFPU] in {
def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst),
@ -2090,19 +2090,19 @@ def STFDX : XForm_28_memOp<31, 727, (outs), (ins f8rc:$frS, memrr:$dst),
let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in {
def STBUX : XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res),
(ins gprc:$rS, memrr:$dst),
"stbux $rS, $dst", IIC_LdStStoreUpd, []>,
"stbux $rS, $dst", IIC_LdStSTUX, []>,
RegConstraint<"$dst.ptrreg = $ea_res">,
NoEncode<"$ea_res">,
PPC970_DGroup_Cracked;
def STHUX : XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res),
(ins gprc:$rS, memrr:$dst),
"sthux $rS, $dst", IIC_LdStStoreUpd, []>,
"sthux $rS, $dst", IIC_LdStSTUX, []>,
RegConstraint<"$dst.ptrreg = $ea_res">,
NoEncode<"$ea_res">,
PPC970_DGroup_Cracked;
def STWUX : XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res),
(ins gprc:$rS, memrr:$dst),
"stwux $rS, $dst", IIC_LdStStoreUpd, []>,
"stwux $rS, $dst", IIC_LdStSTUX, []>,
RegConstraint<"$dst.ptrreg = $ea_res">,
NoEncode<"$ea_res">,
PPC970_DGroup_Cracked;

5
lib/Target/PowerPC/PPCSchedule.td
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@ -42,7 +42,6 @@ def IIC_LdStLoad : InstrItinClass;
def IIC_LdStLoadUpd : InstrItinClass;
def IIC_LdStLoadUpdX : InstrItinClass;
def IIC_LdStStore : InstrItinClass;
def IIC_LdStStoreUpd : InstrItinClass;
def IIC_LdStDSS : InstrItinClass;
def IIC_LdStICBI : InstrItinClass;
def IIC_LdStLD : InstrItinClass;
@ -63,8 +62,8 @@ def IIC_LdStSLBIA : InstrItinClass;
def IIC_LdStSLBIE : InstrItinClass;
def IIC_LdStSTD : InstrItinClass;
def IIC_LdStSTDCX : InstrItinClass;
def IIC_LdStSTDU : InstrItinClass;
def IIC_LdStSTDUX : InstrItinClass;
def IIC_LdStSTU : InstrItinClass;
def IIC_LdStSTUX : InstrItinClass;
def IIC_LdStSTFD : InstrItinClass;
def IIC_LdStSTFDU : InstrItinClass;
def IIC_LdStSTVEBX : InstrItinClass;

11
lib/Target/PowerPC/PPCSchedule440.td
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@ -280,13 +280,6 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<2, [P440_LWB]>],
[1, 1, 1],
[NoBypass, P440_GPR_Bypass]>,
InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_LRACC]>,
InstrStage<1, [P440_AGEN]>,
InstrStage<1, [P440_CRD]>,
InstrStage<2, [P440_LWB]>],
[2, 1, 1, 1],
[NoBypass, P440_GPR_Bypass]>,
InstrItinData<IIC_LdStICBI, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_LRACC]>,
InstrStage<1, [P440_AGEN]>,
@ -373,14 +366,14 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<2, [P440_LWB]>],
[4, 1, 1],
[NoBypass, P440_GPR_Bypass]>,
InstrItinData<IIC_LdStSTDU, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_LdStSTU, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_LRACC]>,
InstrStage<1, [P440_AGEN]>,
InstrStage<1, [P440_CRD]>,
InstrStage<2, [P440_LWB]>],
[2, 1, 1, 1],
[NoBypass, P440_GPR_Bypass]>,
InstrItinData<IIC_LdStSTDUX, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_LdStSTUX, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_LRACC]>,
InstrStage<1, [P440_AGEN]>,
InstrStage<1, [P440_CRD]>,

6
lib/Target/PowerPC/PPCScheduleA2.td
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@ -81,8 +81,6 @@ def PPCA2Itineraries : ProcessorItineraries<
[6, 0, 0]>,
InstrItinData<IIC_LdStStore, [InstrStage<1, [A2_XU]>],
[0, 0, 0]>,
InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [A2_XU]>],
[2, 0, 0, 0]>,
InstrItinData<IIC_LdStICBI, [InstrStage<1, [A2_XU]>],
[16, 0, 0]>,
InstrItinData<IIC_LdStSTFD, [InstrStage<1, [A2_XU]>],
@ -105,9 +103,9 @@ def PPCA2Itineraries : ProcessorItineraries<
[82, 0, 0]>, // L2 latency
InstrItinData<IIC_LdStSTD, [InstrStage<1, [A2_XU]>],
[0, 0, 0]>,
InstrItinData<IIC_LdStSTDU, [InstrStage<1, [A2_XU]>],
InstrItinData<IIC_LdStSTU, [InstrStage<1, [A2_XU]>],
[2, 0, 0, 0]>,
InstrItinData<IIC_LdStSTDUX, [InstrStage<1, [A2_XU]>],
InstrItinData<IIC_LdStSTUX, [InstrStage<1, [A2_XU]>],
[2, 0, 0, 0]>,
InstrItinData<IIC_LdStSTDCX, [InstrStage<1, [A2_XU]>],
[82, 0, 0]>, // L2 latency

8
lib/Target/PowerPC/PPCScheduleE500.td
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@ -144,7 +144,13 @@ def PPCE500Itineraries : ProcessorItineraries<
InstrStage<1, [E500_LSU_0]>],
[6, 1], // Latency = 3
[NoBypass, E500_GPR_Bypass]>,
InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrItinData<IIC_LdStSTU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_SU0, E500_SU1], 0>,
InstrStage<1, [E500_LSU_0]>],
[6, 1], // Latency = 3
[NoBypass, E500_GPR_Bypass],
2>, // 2 micro-ops
InstrItinData<IIC_LdStSTUX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_SU0, E500_SU1], 0>,
InstrStage<1, [E500_LSU_0]>],
[6, 1], // Latency = 3

8
lib/Target/PowerPC/PPCScheduleE500mc.td
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@ -157,7 +157,13 @@ def PPCE500mcItineraries : ProcessorItineraries<
InstrStage<1, [E500mc_LSU_0]>],
[6, 1], // Latency = 3
[NoBypass, E500mc_GPR_Bypass]>,
InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrItinData<IIC_LdStSTU, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,
InstrStage<1, [E500mc_LSU_0]>],
[6, 1], // Latency = 3
[NoBypass, E500mc_GPR_Bypass],
2>, // 2 micro-ops
InstrItinData<IIC_LdStSTUX, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,
InstrStage<1, [E500mc_LSU_0]>],
[6, 1], // Latency = 3

10
lib/Target/PowerPC/PPCScheduleE5500.td
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@ -206,12 +206,6 @@ def PPCE5500Itineraries : ProcessorItineraries<
InstrStage<1, [E5500_LSU_0]>],
[7, 2], // Latency = 3, Repeat rate = 1
[NoBypass, E5500_GPR_Bypass]>,
InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
InstrStage<1, [E5500_LSU_0]>],
[7, 2], // Latency = 3, Repeat rate = 1
[NoBypass, E5500_GPR_Bypass],
2>, // 2 micro-ops
InstrItinData<IIC_LdStICBI, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
InstrStage<1, [E5500_LSU_0]>],
[7, 2], // Latency = 3, Repeat rate = 1
@ -281,13 +275,13 @@ def PPCE5500Itineraries : ProcessorItineraries<
InstrStage<1, [E5500_LSU_0]>],
[7, 2], // Latency = 3, Repeat rate = 1
[NoBypass, E5500_GPR_Bypass]>,
InstrItinData<IIC_LdStSTDU, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
InstrItinData<IIC_LdStSTU, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
InstrStage<1, [E5500_LSU_0]>],
[7, 2], // Latency = 3, Repeat rate = 1
[NoBypass, E5500_GPR_Bypass],
2>, // 2 micro-ops
InstrItinData<IIC_LdStSTDUX, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
InstrItinData<IIC_LdStSTUX, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
InstrStage<1, [E5500_LSU_0]>],
[7, 2], // Latency = 3, Repeat rate = 1

3
lib/Target/PowerPC/PPCScheduleG3.td
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@ -43,7 +43,8 @@ def G3Itineraries : ProcessorItineraries<
InstrItinData<IIC_LdStLoadUpd , [InstrStage<2, [G3_SLU]>]>,
InstrItinData<IIC_LdStLoadUpdX, [InstrStage<2, [G3_SLU]>]>,
InstrItinData<IIC_LdStStore , [InstrStage<2, [G3_SLU]>]>,
InstrItinData<IIC_LdStStoreUpd, [InstrStage<2, [G3_SLU]>]>,
InstrItinData<IIC_LdStSTU , [InstrStage<2, [G3_SLU]>]>,
InstrItinData<IIC_LdStSTUX , [InstrStage<2, [G3_SLU]>]>,
InstrItinData<IIC_LdStICBI , [InstrStage<3, [G3_SLU]>]>,
InstrItinData<IIC_LdStSTFD , [InstrStage<2, [G3_SLU]>]>,
InstrItinData<IIC_LdStSTFDU , [InstrStage<2, [G3_SLU]>]>,

3
lib/Target/PowerPC/PPCScheduleG4.td
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@ -48,7 +48,8 @@ def G4Itineraries : ProcessorItineraries<
InstrItinData<IIC_LdStLoadUpd , [InstrStage<2, [G4_SLU]>]>,
InstrItinData<IIC_LdStLoadUpdX, [InstrStage<2, [G4_SLU]>]>,
InstrItinData<IIC_LdStStore , [InstrStage<2, [G4_SLU]>]>,
InstrItinData<IIC_LdStStoreUpd, [InstrStage<2, [G4_SLU]>]>,
InstrItinData<IIC_LdStSTU , [InstrStage<2, [G4_SLU]>]>,
InstrItinData<IIC_LdStSTUX , [InstrStage<2, [G4_SLU]>]>,
InstrItinData<IIC_LdStDSS , [InstrStage<2, [G4_SLU]>]>,
InstrItinData<IIC_LdStICBI , [InstrStage<2, [G4_SLU]>]>,
InstrItinData<IIC_LdStSTFD , [InstrStage<2, [G4_SLU]>]>,

5
lib/Target/PowerPC/PPCScheduleG4Plus.td
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@ -56,7 +56,6 @@ def G4PlusItineraries : ProcessorItineraries<
InstrItinData<IIC_LdStLoadUpd , [InstrStage<3, [G4P_SLU]>]>,
InstrItinData<IIC_LdStLoadUpdX, [InstrStage<3, [G4P_SLU]>]>,
InstrItinData<IIC_LdStStore , [InstrStage<3, [G4P_SLU]>]>,
InstrItinData<IIC_LdStStoreUpd, [InstrStage<3, [G4P_SLU]>]>,
InstrItinData<IIC_LdStDSS , [InstrStage<3, [G4P_SLU]>]>,
InstrItinData<IIC_LdStICBI , [InstrStage<3, [G4P_IU2]>]>,
InstrItinData<IIC_LdStSTFD , [InstrStage<3, [G4P_SLU]>]>,
@ -73,8 +72,8 @@ def G4PlusItineraries : ProcessorItineraries<
InstrItinData<IIC_LdStLWARX , [InstrStage<3, [G4P_SLU]>]>,
InstrItinData<IIC_LdStSTD , [InstrStage<3, [G4P_SLU]>]>,
InstrItinData<IIC_LdStSTDCX , [InstrStage<3, [G4P_SLU]>]>,
InstrItinData<IIC_LdStSTDU , [InstrStage<3, [G4P_SLU]>]>,
InstrItinData<IIC_LdStSTDUX , [InstrStage<3, [G4P_SLU]>]>,
InstrItinData<IIC_LdStSTU , [InstrStage<3, [G4P_SLU]>]>,
InstrItinData<IIC_LdStSTUX , [InstrStage<3, [G4P_SLU]>]>,
InstrItinData<IIC_LdStSTVEBX , [InstrStage<3, [G4P_SLU]>]>,
InstrItinData<IIC_LdStSTWCX , [InstrStage<3, [G4P_SLU]>]>,
InstrItinData<IIC_LdStSync , [InstrStage<35, [G4P_SLU]>]>,

5
lib/Target/PowerPC/PPCScheduleG5.td
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@ -54,7 +54,6 @@ def G5Itineraries : ProcessorItineraries<
InstrItinData<IIC_LdStLoadUpd , [InstrStage<3, [G5_SLU]>]>,
InstrItinData<IIC_LdStLoadUpdX, [InstrStage<3, [G5_SLU]>]>,
InstrItinData<IIC_LdStStore , [InstrStage<3, [G5_SLU]>]>,
InstrItinData<IIC_LdStStoreUpd, [InstrStage<3, [G5_SLU]>]>,
InstrItinData<IIC_LdStDSS , [InstrStage<10, [G5_SLU]>]>,
InstrItinData<IIC_LdStICBI , [InstrStage<40, [G5_SLU]>]>,
InstrItinData<IIC_LdStSTFD , [InstrStage<4, [G5_SLU]>]>,
@ -76,8 +75,8 @@ def G5Itineraries : ProcessorItineraries<
InstrItinData<IIC_LdStSLBIA , [InstrStage<40, [G5_SLU]>]>, // needs work
InstrItinData<IIC_LdStSLBIE , [InstrStage<2, [G5_SLU]>]>,
InstrItinData<IIC_LdStSTD , [InstrStage<3, [G5_SLU]>]>,
InstrItinData<IIC_LdStSTDU , [InstrStage<3, [G5_SLU]>]>,
InstrItinData<IIC_LdStSTDUX , [InstrStage<3, [G5_SLU]>]>,
InstrItinData<IIC_LdStSTU , [InstrStage<3, [G5_SLU]>]>,
InstrItinData<IIC_LdStSTUX , [InstrStage<3, [G5_SLU]>]>,
InstrItinData<IIC_LdStSTDCX , [InstrStage<11, [G5_SLU]>]>,
InstrItinData<IIC_LdStSTVEBX , [InstrStage<5, [G5_SLU]>]>,
InstrItinData<IIC_LdStSTWCX , [InstrStage<11, [G5_SLU]>]>,

4
lib/Target/PowerPC/PPCScheduleP7.td
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@ -261,13 +261,13 @@ def P7Itineraries : ProcessorItineraries<
InstrStage<1, [P7_LS1, P7_LS2], 0>,
InstrStage<1, [P7_FX1, P7_FX2]>],
[1, 1, 1]>,
InstrItinData<IIC_LdStSTDU , [InstrStage<1, [P7_DU1], 0>,
InstrItinData<IIC_LdStSTU , [InstrStage<1, [P7_DU1], 0>,
InstrStage<1, [P7_DU2], 0>,
InstrStage<1, [P7_LS1, P7_LS2], 0>,
InstrStage<1, [P7_FX1, P7_FX2]>,
InstrStage<1, [P7_FX1, P7_FX2]>],
[2, 1, 1, 1]>,
InstrItinData<IIC_LdStSTDUX , [InstrStage<1, [P7_DU1], 0>,
InstrItinData<IIC_LdStSTUX , [InstrStage<1, [P7_DU1], 0>,
InstrStage<1, [P7_DU2], 0>,
InstrStage<1, [P7_DU3], 0>,
InstrStage<1, [P7_DU4], 0>,

4
lib/Target/PowerPC/PPCScheduleP8.td
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@ -267,14 +267,14 @@ def P8Itineraries : ProcessorItineraries<
InstrStage<1, [P8_LU1, P8_LU2,
P8_LSU1, P8_LSU2]>]
[1, 1, 1]>,
InstrItinData<IIC_LdStSTDU , [InstrStage<1, [P8_DU1], 0>,
InstrItinData<IIC_LdStSTU , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_DU2], 0>,
InstrStage<1, [P8_LU1, P8_LU2,
P8_LSU1, P8_LSU2], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[2, 1, 1, 1]>,
// First+last
InstrItinData<IIC_LdStSTDUX , [InstrStage<1, [P8_DU1], 0>,
InstrItinData<IIC_LdStSTUX , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_DU2], 0>,
InstrStage<1, [P8_DU3], 0>,
InstrStage<1, [P8_DU4], 0>,

4
test/CodeGen/PowerPC/stwu-sched.ll
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@ -15,8 +15,8 @@ define void @initCombList(%0* nocapture, i32 signext) local_unnamed_addr #0 {
; CHECK-NEXT: stwu 5, 64(4)
; CHECK-ITIN-LABEL: initCombList:
; CHECK-ITIN: addi 3, 3, -8
; CHECK-ITIN-NEXT: stwu 5, 64(4)
; CHECK-ITIN: stwu 5, 64(4)
; CHECK-ITIN-NEXT: addi 3, 3, -8
%3 = zext i32 %1 to i64