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[AArch64] Use a static function and other minor cleanup for readability. NFC.
llvm-svn: 244233
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766ef3c94f
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@ -134,9 +134,6 @@ struct AArch64LoadStoreOpt : public MachineFunctionPass {
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const char *getPassName() const override {
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const char *getPassName() const override {
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return AARCH64_LOAD_STORE_OPT_NAME;
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return AARCH64_LOAD_STORE_OPT_NAME;
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}
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}
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private:
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int getMemSize(MachineInstr *MemMI);
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};
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};
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char AArch64LoadStoreOpt::ID = 0;
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char AArch64LoadStoreOpt::ID = 0;
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} // namespace
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} // namespace
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@ -144,7 +141,7 @@ char AArch64LoadStoreOpt::ID = 0;
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INITIALIZE_PASS(AArch64LoadStoreOpt, "aarch64-ldst-opt",
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INITIALIZE_PASS(AArch64LoadStoreOpt, "aarch64-ldst-opt",
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AARCH64_LOAD_STORE_OPT_NAME, false, false)
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AARCH64_LOAD_STORE_OPT_NAME, false, false)
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static bool isUnscaledLdst(unsigned Opc) {
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static bool isUnscaledLdSt(unsigned Opc) {
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switch (Opc) {
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switch (Opc) {
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default:
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default:
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return false;
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return false;
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@ -163,9 +160,13 @@ static bool isUnscaledLdst(unsigned Opc) {
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}
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}
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}
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}
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static bool isUnscaledLdSt(MachineInstr *MI) {
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return isUnscaledLdSt(MI->getOpcode());
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}
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// Size in bytes of the data moved by an unscaled load or store
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// Size in bytes of the data moved by an unscaled load or store
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int AArch64LoadStoreOpt::getMemSize(MachineInstr *MemMI) {
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static int getMemSize(MachineInstr *MI) {
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switch (MemMI->getOpcode()) {
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switch (MI->getOpcode()) {
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default:
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default:
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llvm_unreachable("Opcode has unknown size!");
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llvm_unreachable("Opcode has unknown size!");
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case AArch64::STRSui:
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case AArch64::STRSui:
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@ -367,7 +368,7 @@ AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
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int SExtIdx = Flags.getSExtIdx();
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int SExtIdx = Flags.getSExtIdx();
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unsigned Opc =
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unsigned Opc =
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SExtIdx == -1 ? I->getOpcode() : getMatchingNonSExtOpcode(I->getOpcode());
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SExtIdx == -1 ? I->getOpcode() : getMatchingNonSExtOpcode(I->getOpcode());
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bool IsUnscaled = isUnscaledLdst(Opc);
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bool IsUnscaled = isUnscaledLdSt(Opc);
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int OffsetStride =
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int OffsetStride =
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IsUnscaled && EnableAArch64UnscaledMemOp ? getMemSize(I) : 1;
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IsUnscaled && EnableAArch64UnscaledMemOp ? getMemSize(I) : 1;
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@ -547,7 +548,7 @@ AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
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unsigned Opc = FirstMI->getOpcode();
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unsigned Opc = FirstMI->getOpcode();
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bool MayLoad = FirstMI->mayLoad();
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bool MayLoad = FirstMI->mayLoad();
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bool IsUnscaled = isUnscaledLdst(Opc);
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bool IsUnscaled = isUnscaledLdSt(FirstMI);
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unsigned Reg = getLdStRegOp(FirstMI).getReg();
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unsigned Reg = getLdStRegOp(FirstMI).getReg();
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unsigned BaseReg = getLdStBaseOp(FirstMI).getReg();
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unsigned BaseReg = getLdStBaseOp(FirstMI).getReg();
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int Offset = getLdStOffsetOp(FirstMI).getImm();
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int Offset = getLdStOffsetOp(FirstMI).getImm();
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@ -618,7 +619,7 @@ AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
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return E;
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return E;
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// If the resultant immediate offset of merging these instructions
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// If the resultant immediate offset of merging these instructions
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// is out of range for a pairwise instruction, bail and keep looking.
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// is out of range for a pairwise instruction, bail and keep looking.
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bool MIIsUnscaled = isUnscaledLdst(MI->getOpcode());
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bool MIIsUnscaled = isUnscaledLdSt(MI);
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if (!inBoundsForPair(MIIsUnscaled, MinOffset, OffsetStride)) {
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if (!inBoundsForPair(MIIsUnscaled, MinOffset, OffsetStride)) {
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trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
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trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
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if (MI->mayLoadOrStore())
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if (MI->mayLoadOrStore())
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@ -995,7 +996,7 @@ bool AArch64LoadStoreOpt::optimizeBlock(MachineBasicBlock &MBB) {
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Modified = true;
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Modified = true;
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++NumPairCreated;
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++NumPairCreated;
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if (isUnscaledLdst(MI->getOpcode()))
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if (isUnscaledLdSt(MI))
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++NumUnscaledPairCreated;
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++NumUnscaledPairCreated;
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break;
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break;
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}
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}
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@ -1055,7 +1056,7 @@ bool AArch64LoadStoreOpt::optimizeBlock(MachineBasicBlock &MBB) {
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}
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}
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// Don't know how to handle pre/post-index versions, so move to the next
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// Don't know how to handle pre/post-index versions, so move to the next
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// instruction.
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// instruction.
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if (isUnscaledLdst(Opc)) {
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if (isUnscaledLdSt(Opc)) {
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++MBBI;
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++MBBI;
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break;
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break;
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}
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}
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