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[AArch64] Add support for NEON scalar three register different instruction

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class.  The instruction class includes the signed saturating doubling
multiply-add long, signed saturating doubling multiply-subtract long, and
the signed saturating doubling multiply long instructions.

llvm-svn: 192908
This commit is contained in:
Chad Rosier 2013-10-17 18:12:29 +00:00
parent 4e9662d96e
commit 9a6d485c7f
7 changed files with 237 additions and 0 deletions
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9
include/llvm/IR/IntrinsicsAArch64.td
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@ -204,4 +204,13 @@ def int_aarch64_neon_vabs :
// Scalar Negate Value
def int_aarch64_neon_vneg :
Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty], [IntrNoMem]>;
// Signed Saturating Doubling Multiply-Add Long
def int_aarch64_neon_vqdmlal : Neon_2Arg_Long_Intrinsic;
// Signed Saturating Doubling Multiply-Subtract Long
def int_aarch64_neon_vqdmlsl : Neon_2Arg_Long_Intrinsic;
// Signed Saturating Doubling Multiply Long
def int_aarch64_neon_vqdmull : Neon_2Arg_Long_Intrinsic;
}

18
lib/Target/AArch64/AArch64InstrFormats.td
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@ -1212,5 +1212,23 @@ class NeonI_LdStMult<bit q, bit l, bits<4> opcode, bits<2> size,
// Inherit Rt in 4-0
}
// Format AdvSIMD 3 scalar registers with different type
class NeonI_Scalar3Diff<bit u, bits<2> size, bits<4> opcode,
dag outs, dag ins, string asmstr,
list<dag> patterns, InstrItinClass itin>
: A64InstRdnm<outs, ins, asmstr, patterns, itin> {
let Inst{31-30} = 0b01;
let Inst{29} = u;
let Inst{28-24} = 0b11110;
let Inst{23-22} = size;
let Inst{21} = 0b1;
// Inherit Rm in 20-16
let Inst{15-12} = opcode;
let Inst{11-10} = 0b00;
// Inherit Rn in 9-5
// Inherit Rd in 4-0
}
}

39
lib/Target/AArch64/AArch64InstrNEON.td
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@ -3231,6 +3231,30 @@ multiclass Neon_Scalar3Same_SD_size_patterns<SDPatternOperator opnode,
(INSTD FPR64:$Rn, FPR64:$Rm)>;
}
// Scalar Three Different
multiclass NeonI_Scalar3Diff_HS_size<bit u, bits<4> opcode, string asmop> {
def shh : NeonI_Scalar3Diff<u, 0b01, opcode,
(outs FPR32:$Rd), (ins FPR16:$Rn, FPR16:$Rm),
!strconcat(asmop, " $Rd, $Rn, $Rm"),
[],
NoItinerary>;
def dss : NeonI_Scalar3Diff<u, 0b10, opcode,
(outs FPR64:$Rd), (ins FPR32:$Rn, FPR32:$Rm),
!strconcat(asmop, " $Rd, $Rn, $Rm"),
[],
NoItinerary>;
}
multiclass Neon_Scalar3Diff_HS_size_patterns<SDPatternOperator opnode,
Instruction INSTH,
Instruction INSTS> {
def : Pat<(v1i32 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
(INSTH FPR16:$Rn, FPR16:$Rm)>;
def : Pat<(v1i64 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
(INSTS FPR32:$Rn, FPR32:$Rm)>;
}
// Scalar Two Registers Miscellaneous
multiclass NeonI_Scalar2SameMisc_SD_size<bit u, bit size_high, bits<5> opcode,
@ -3498,6 +3522,21 @@ defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqrshlu, UQRSHLbbb,
defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqrshifts, SQRSHLddd>;
defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqrshiftu, UQRSHLddd>;
// Signed Saturating Doubling Multiply-Add Long
defm SQDMLAL : NeonI_Scalar3Diff_HS_size<0b0, 0b1001, "sqdmlal">;
defm : Neon_Scalar3Diff_HS_size_patterns<int_aarch64_neon_vqdmlal,
SQDMLALshh, SQDMLALdss>;
// Signed Saturating Doubling Multiply-Subtract Long
defm SQDMLSL : NeonI_Scalar3Diff_HS_size<0b0, 0b1011, "sqdmlsl">;
defm : Neon_Scalar3Diff_HS_size_patterns<int_aarch64_neon_vqdmlsl,
SQDMLSLshh, SQDMLSLdss>;
// Signed Saturating Doubling Multiply Long
defm SQDMULL : NeonI_Scalar3Diff_HS_size<0b0, 0b1101, "sqdmull">;
defm : Neon_Scalar3Diff_HS_size_patterns<int_aarch64_neon_vqdmull,
SQDMULLshh, SQDMULLdss>;
// Scalar Signed Integer Convert To Floating-point
defm SCVTF : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11101, "scvtf">;
defm : Neon_Scalar2SameMisc_cvt_SD_size_patterns<int_aarch64_neon_vcvtf32_s32,

75
test/CodeGen/AArch64/neon-scalar-mul.ll
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@ -68,3 +68,78 @@ define double @test_vmulxd_f64(double %a, double %b) {
declare <1 x float> @llvm.aarch64.neon.vmulx.v1f32(<1 x float>, <1 x float>)
declare <1 x double> @llvm.aarch64.neon.vmulx.v1f64(<1 x double>, <1 x double>)
define i32 @test_vqdmlalh_s16(i16 %a, i16 %b) {
; CHECK: test_vqdmlalh_s16
; CHECK: sqdmlal {{s[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
entry:
%vqdmlal.i = insertelement <1 x i16> undef, i16 %a, i32 0
%vqdmlal1.i = insertelement <1 x i16> undef, i16 %b, i32 0
%vqdmlal2.i = call <1 x i32> @llvm.aarch64.neon.vqdmlal.v1i32(<1 x i16> %vqdmlal.i, <1 x i16> %vqdmlal1.i)
%0 = extractelement <1 x i32> %vqdmlal2.i, i32 0
ret i32 %0
}
define i64 @test_vqdmlals_s32(i32 %a, i32 %b) {
; CHECK: test_vqdmlals_s32
; CHECK: sqdmlal {{d[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
entry:
%vqdmlal.i = insertelement <1 x i32> undef, i32 %a, i32 0
%vqdmlal1.i = insertelement <1 x i32> undef, i32 %b, i32 0
%vqdmlal2.i = call <1 x i64> @llvm.aarch64.neon.vqdmlal.v1i64(<1 x i32> %vqdmlal.i, <1 x i32> %vqdmlal1.i)
%0 = extractelement <1 x i64> %vqdmlal2.i, i32 0
ret i64 %0
}
declare <1 x i32> @llvm.aarch64.neon.vqdmlal.v1i32(<1 x i16>, <1 x i16>)
declare <1 x i64> @llvm.aarch64.neon.vqdmlal.v1i64(<1 x i32>, <1 x i32>)
define i32 @test_vqdmlslh_s16(i16 %a, i16 %b) {
; CHECK: test_vqdmlslh_s16
; CHECK: sqdmlsl {{s[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
entry:
%vqdmlsl.i = insertelement <1 x i16> undef, i16 %a, i32 0
%vqdmlsl1.i = insertelement <1 x i16> undef, i16 %b, i32 0
%vqdmlsl2.i = call <1 x i32> @llvm.aarch64.neon.vqdmlsl.v1i32(<1 x i16> %vqdmlsl.i, <1 x i16> %vqdmlsl1.i)
%0 = extractelement <1 x i32> %vqdmlsl2.i, i32 0
ret i32 %0
}
define i64 @test_vqdmlsls_s32(i32 %a, i32 %b) {
; CHECK: test_vqdmlsls_s32
; CHECK: sqdmlsl {{d[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
entry:
%vqdmlsl.i = insertelement <1 x i32> undef, i32 %a, i32 0
%vqdmlsl1.i = insertelement <1 x i32> undef, i32 %b, i32 0
%vqdmlsl2.i = call <1 x i64> @llvm.aarch64.neon.vqdmlsl.v1i64(<1 x i32> %vqdmlsl.i, <1 x i32> %vqdmlsl1.i)
%0 = extractelement <1 x i64> %vqdmlsl2.i, i32 0
ret i64 %0
}
declare <1 x i32> @llvm.aarch64.neon.vqdmlsl.v1i32(<1 x i16>, <1 x i16>)
declare <1 x i64> @llvm.aarch64.neon.vqdmlsl.v1i64(<1 x i32>, <1 x i32>)
define i32 @test_vqdmullh_s16(i16 %a, i16 %b) {
; CHECK: test_vqdmullh_s16
; CHECK: sqdmull {{s[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
entry:
%vqdmull.i = insertelement <1 x i16> undef, i16 %a, i32 0
%vqdmull1.i = insertelement <1 x i16> undef, i16 %b, i32 0
%vqdmull2.i = call <1 x i32> @llvm.aarch64.neon.vqdmull.v1i32(<1 x i16> %vqdmull.i, <1 x i16> %vqdmull1.i)
%0 = extractelement <1 x i32> %vqdmull2.i, i32 0
ret i32 %0
}
define i64 @test_vqdmulls_s32(i32 %a, i32 %b) {
; CHECK: test_vqdmulls_s32
; CHECK: sqdmull {{d[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
entry:
%vqdmull.i = insertelement <1 x i32> undef, i32 %a, i32 0
%vqdmull1.i = insertelement <1 x i32> undef, i32 %b, i32 0
%vqdmull2.i = call <1 x i64> @llvm.aarch64.neon.vqdmull.v1i64(<1 x i32> %vqdmull.i, <1 x i32> %vqdmull1.i)
%0 = extractelement <1 x i64> %vqdmull2.i, i32 0
ret i64 %0
}
declare <1 x i32> @llvm.aarch64.neon.vqdmull.v1i32(<1 x i16>, <1 x i16>)
declare <1 x i64> @llvm.aarch64.neon.vqdmull.v1i64(<1 x i32>, <1 x i32>)

42
test/MC/AArch64/neon-diagnostics.s
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@ -4460,3 +4460,45 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: neg d29, s24
// CHECK-ERROR: ^
//----------------------------------------------------------------------
// Signed Saturating Doubling Multiply-Add Long
//----------------------------------------------------------------------
sqdmlal s17, h27, s12
sqdmlal d19, s24, d12
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: sqdmlal s17, h27, s12
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: sqdmlal d19, s24, d12
// CHECK-ERROR: ^
//----------------------------------------------------------------------
// Signed Saturating Doubling Multiply-Subtract Long
//----------------------------------------------------------------------
sqdmlsl s14, h12, s25
sqdmlsl d12, s23, d13
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: sqdmlsl s14, h12, s25
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: sqdmlsl d12, s23, d13
// CHECK-ERROR: ^
//----------------------------------------------------------------------
// Signed Saturating Doubling Multiply Long
//----------------------------------------------------------------------
sqdmull s12, h22, s12
sqdmull d15, s22, d12
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: sqdmull s12, h22, s12
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: sqdmull d15, s22, d12
// CHECK-ERROR: ^

30
test/MC/AArch64/neon-scalar-mul.s
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@ -31,3 +31,33 @@
// CHECK: fmulx s20, s22, s15 // encoding: [0xd4,0xde,0x2f,0x5e]
// CHECK: fmulx d23, d11, d1 // encoding: [0x77,0xdd,0x61,0x5e]
//----------------------------------------------------------------------
// Signed Saturating Doubling Multiply-Add Long
//----------------------------------------------------------------------
sqdmlal s17, h27, h12
sqdmlal d19, s24, s12
// CHECK: sqdmlal s17, h27, h12 // encoding: [0x71,0x93,0x6c,0x5e]
// CHECK: sqdmlal d19, s24, s12 // encoding: [0x13,0x93,0xac,0x5e]
//----------------------------------------------------------------------
// Signed Saturating Doubling Multiply-Subtract Long
//----------------------------------------------------------------------
sqdmlsl s14, h12, h25
sqdmlsl d12, s23, s13
// CHECK: sqdmlsl s14, h12, h25 // encoding: [0x8e,0xb1,0x79,0x5e]
// CHECK: sqdmlsl d12, s23, s13 // encoding: [0xec,0xb2,0xad,0x5e]
//----------------------------------------------------------------------
// Signed Saturating Doubling Multiply Long
//----------------------------------------------------------------------
sqdmull s12, h22, h12
sqdmull d15, s22, s12
// CHECK: sqdmull s12, h22, h12 // encoding: [0xcc,0xd2,0x6c,0x5e]
// CHECK: sqdmull d15, s22, s12 // encoding: [0xcf,0xd2,0xac,0x5e]

24
test/MC/Disassembler/AArch64/neon-instructions.txt
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@ -1659,3 +1659,27 @@
0xf4,0x39,0x60,0x7e
0x95,0x39,0xa0,0x7e
0xd2,0x3a,0xe0,0x7e
#----------------------------------------------------------------------
# Signed Saturating Doubling Multiply-Add Long
#----------------------------------------------------------------------
# CHECK: sqdmlal s17, h27, h12
# CHECK: sqdmlal d19, s24, s12
0x71,0x93,0x6c,0x5e
0x13,0x93,0xac,0x5e
#----------------------------------------------------------------------
# Signed Saturating Doubling Multiply-Subtract Long
#----------------------------------------------------------------------
# CHECK: sqdmlsl s14, h12, h25
# CHECK: sqdmlsl d12, s23, s13
0x8e,0xb1,0x79,0x5e
0xec,0xb2,0xad,0x5e
#----------------------------------------------------------------------
# Signed Saturating Doubling Multiply Long
#----------------------------------------------------------------------
# CHECK: sqdmull s12, h22, h12
# CHECK: sqdmull d15, s22, s12
0xcc,0xd2,0x6c,0x5e
0xcf,0xd2,0xac,0x5e