RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-21 03:53:04 +02:00
Code Issues Projects Releases Wiki Activity

Fix PR 10635. When generating integer constants, the constant element type may

Browse Source 
be illegal, even if the requested vector type is legal. Testcase is one of the
disabled ARM tests in the vector-select patch.

llvm-svn: 137562
This commit is contained in:
Nadav Rotem 2011-08-13 20:31:45 +00:00
parent 1dc4fa369c
commit 9a776ed9cd
1 changed files with 7 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -928,6 +928,13 @@ SDValue SelectionDAG::getConstant(const ConstantInt &Val, EVT VT, bool isT) {
assert(Val.getBitWidth() == EltVT.getSizeInBits() &&
"APInt size does not match type size!");
// In some cases the vector type is legal but the element type is illegal.
// In this case, promote the inserted value. The type does not need to match
// the vector element type. Any extra bits introduced will be
// truncated away.
if (VT.isVector())
EltVT = TLI.getTypeToTransformTo(*getContext(), EltVT);
unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant;
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0);