RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-19 02:52:53 +02:00
Code Issues Projects Releases Wiki Activity

Use IndexedMap for MachineRegisterInfo as well. No functional change.

Browse Source 
llvm-svn: 123106
This commit is contained in:
Jakob Stoklund Olesen 2011-01-09 03:05:46 +00:00
parent 57e9b35653
commit 9a7e67d141
3 changed files with 34 additions and 35 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
include/llvm/ADT/IndexedMap.h
View File

@ -55,6 +55,10 @@ namespace llvm {
return storage_[toIndex_(n)];
}
void reserve(typename StorageT::size_type s) {
storage_.reserve(s);
}
void clear() {
storage_.clear();
}

22
include/llvm/CodeGen/MachineRegisterInfo.h
View File

@ -16,6 +16,7 @@
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/IndexedMap.h"
#include <vector>
namespace llvm {
@ -24,13 +25,12 @@ namespace llvm {
/// registers, including vreg register classes, use/def chains for registers,
/// etc.
class MachineRegisterInfo {
/// VRegInfo - Information we keep for each virtual register. The entries in
/// this vector are actually converted to vreg numbers by adding the
/// TargetRegisterInfo::FirstVirtualRegister delta to their index.
/// VRegInfo - Information we keep for each virtual register.
///
/// Each element in this list contains the register class of the vreg and the
/// start of the use/def list for the register.
std::vector<std::pair<const TargetRegisterClass*, MachineOperand*> > VRegInfo;
IndexedMap<std::pair<const TargetRegisterClass*, MachineOperand*>,
VirtReg2IndexFunctor> VRegInfo;
/// RegClassVRegMap - This vector acts as a map from TargetRegisterClass to
/// virtual registers. For each target register class, it keeps a list of
@ -44,7 +44,7 @@ class MachineRegisterInfo {
/// register for allocation. For example, if the hint is <0, 1024>, it means
/// the allocator should prefer the physical register allocated to the virtual
/// register of the hint.
std::vector<std::pair<unsigned, unsigned> > RegAllocHints;
IndexedMap<std::pair<unsigned, unsigned>, VirtReg2IndexFunctor> RegAllocHints;
/// PhysRegUseDefLists - This is an array of the head of the use/def list for
/// physical registers.
@ -159,16 +159,14 @@ public:
/// getRegUseDefListHead - Return the head pointer for the register use/def
/// list for the specified virtual or physical register.
MachineOperand *&getRegUseDefListHead(unsigned RegNo) {
if (RegNo < TargetRegisterInfo::FirstVirtualRegister)
if (!RegNo || TargetRegisterInfo::isPhysicalRegister(RegNo))
return PhysRegUseDefLists[RegNo];
RegNo -= TargetRegisterInfo::FirstVirtualRegister;
return VRegInfo[RegNo].second;
}
MachineOperand *getRegUseDefListHead(unsigned RegNo) const {
if (RegNo < TargetRegisterInfo::FirstVirtualRegister)
if (!RegNo || TargetRegisterInfo::isPhysicalRegister(RegNo))
return PhysRegUseDefLists[RegNo];
RegNo -= TargetRegisterInfo::FirstVirtualRegister;
return VRegInfo[RegNo].second;
}
@ -194,8 +192,6 @@ public:
/// getRegClass - Return the register class of the specified virtual register.
///
const TargetRegisterClass *getRegClass(unsigned Reg) const {
Reg -= TargetRegisterInfo::FirstVirtualRegister;
assert(Reg < VRegInfo.size() && "Invalid vreg!");
return VRegInfo[Reg].first;
}
@ -236,8 +232,6 @@ public:
/// setRegAllocationHint - Specify a register allocation hint for the
/// specified virtual register.
void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) {
Reg -= TargetRegisterInfo::FirstVirtualRegister;
assert(Reg < VRegInfo.size() && "Invalid vreg!");
RegAllocHints[Reg].first = Type;
RegAllocHints[Reg].second = PrefReg;
}
@ -246,8 +240,6 @@ public:
/// specified virtual register.
std::pair<unsigned, unsigned>
getRegAllocationHint(unsigned Reg) const {
Reg -= TargetRegisterInfo::FirstVirtualRegister;
assert(Reg < VRegInfo.size() && "Invalid vreg!");
return RegAllocHints[Reg];
}

43
lib/CodeGen/MachineRegisterInfo.cpp
View File

@ -30,8 +30,9 @@ MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) {
MachineRegisterInfo::~MachineRegisterInfo() {
#ifndef NDEBUG
for (unsigned i = 0, e = VRegInfo.size(); i != e; ++i)
assert(VRegInfo[i].second == 0 && "Vreg use list non-empty still?");
for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i)
assert(VRegInfo[TargetRegisterInfo::index2VirtReg(i)].second == 0 &&
"Vreg use list non-empty still?");
for (unsigned i = 0, e = UsedPhysRegs.size(); i != e; ++i)
assert(!PhysRegUseDefLists[i] &&
"PhysRegUseDefLists has entries after all instructions are deleted");
@ -44,20 +45,18 @@ MachineRegisterInfo::~MachineRegisterInfo() {
///
void
MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
unsigned VR = Reg;
Reg -= TargetRegisterInfo::FirstVirtualRegister;
assert(Reg < VRegInfo.size() && "Invalid vreg!");
const TargetRegisterClass *OldRC = VRegInfo[Reg].first;
VRegInfo[Reg].first = RC;
// Remove from old register class's vregs list. This may be slow but
// fortunately this operation is rarely needed.
std::vector<unsigned> &VRegs = RegClass2VRegMap[OldRC->getID()];
std::vector<unsigned>::iterator I = std::find(VRegs.begin(), VRegs.end(), VR);
std::vector<unsigned>::iterator I =
std::find(VRegs.begin(), VRegs.end(), Reg);
VRegs.erase(I);
// Add to new register class's vregs list.
RegClass2VRegMap[RC->getID()].push_back(VR);
RegClass2VRegMap[RC->getID()].push_back(Reg);
}
const TargetRegisterClass *
@ -80,17 +79,22 @@ MachineRegisterInfo::constrainRegClass(unsigned Reg,
unsigned
MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){
assert(RegClass && "Cannot create register without RegClass!");
// Add a reg, but keep track of whether the vector reallocated or not.
void *ArrayBase = VRegInfo.empty() ? 0 : &VRegInfo[0];
VRegInfo.push_back(std::make_pair(RegClass, (MachineOperand*)0));
RegAllocHints.push_back(std::make_pair(0, 0));
if (!((&VRegInfo[0] == ArrayBase || VRegInfo.size() == 1)))
// New virtual register number.
unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs());
// Add a reg, but keep track of whether the vector reallocated or not.
const unsigned FirstVirtReg = TargetRegisterInfo::index2VirtReg(0);
void *ArrayBase = getNumVirtRegs() == 0 ? 0 : &VRegInfo[FirstVirtReg];
VRegInfo.grow(Reg);
VRegInfo[Reg].first = RegClass;
RegAllocHints.grow(Reg);
if (ArrayBase && &VRegInfo[FirstVirtReg] != ArrayBase)
// The vector reallocated, handle this now.
HandleVRegListReallocation();
unsigned VR = getLastVirtReg();
RegClass2VRegMap[RegClass->getID()].push_back(VR);
return VR;
RegClass2VRegMap[RegClass->getID()].push_back(Reg);
return Reg;
}
/// HandleVRegListReallocation - We just added a virtual register to the
@ -99,11 +103,12 @@ MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){
void MachineRegisterInfo::HandleVRegListReallocation() {
// The back pointers for the vreg lists point into the previous vector.
// Update them to point to their correct slots.
for (unsigned i = 0, e = VRegInfo.size(); i != e; ++i) {
MachineOperand *List = VRegInfo[i].second;
for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) {
unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
MachineOperand *List = VRegInfo[Reg].second;
if (!List) continue;
// Update the back-pointer to be accurate once more.
List->Contents.Reg.Prev = &VRegInfo[i].second;
List->Contents.Reg.Prev = &VRegInfo[Reg].second;
}
}
@ -126,8 +131,6 @@ void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) {
/// register or null if none is found. This assumes that the code is in SSA
/// form, so there should only be one definition.
MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const {
assert(Reg-TargetRegisterInfo::FirstVirtualRegister < VRegInfo.size() &&
"Invalid vreg!");
// Since we are in SSA form, we can use the first definition.
if (!def_empty(Reg))
return &*def_begin(Reg);