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llvm-mc/X86: Implement single instruction encoding interface for MC.
- Note, this is a gigantic hack, with the sole purpose of unblocking further work on the assembler (its also possible to test the mathcer more completely now). - Despite being a hack, its actually good enough to work over all of 403.gcc (although some encodings are probably incorrect). This is a testament to the beauty of X86's MachineInstr, no doubt! ;) llvm-svn: 80234
This commit is contained in:
Daniel Dunbar
parent
b11e3eb82f
commit
9a8ec155f7
@ -22,7 +22,9 @@ namespace llvm {
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class X86TargetMachine;
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class FunctionPass;
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class MachineCodeEmitter;
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class MCCodeEmitter;
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class JITCodeEmitter;
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class Target;
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class formatted_raw_ostream;
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/// createX86ISelDag - This pass converts a legalized DAG into a
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@ -52,6 +54,8 @@ FunctionPass *createX86JITCodeEmitterPass(X86TargetMachine &TM,
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FunctionPass *createX86ObjectCodeEmitterPass(X86TargetMachine &TM,
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ObjectCodeEmitter &OCE);
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MCCodeEmitter *createX86MCCodeEmitter(const Target &, TargetMachine &TM);
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/// createX86EmitCodeToMemory - Returns a pass that converts a register
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/// allocated function into raw machine code in a dynamically
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/// allocated chunk of memory.
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@ -29,6 +29,8 @@
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Function.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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@ -858,3 +860,251 @@ void Emitter<CodeEmitter>::emitInstruction(const MachineInstr &MI,
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llvm_unreachable(0);
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}
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}
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// Adapt the Emitter / CodeEmitter interfaces to MCCodeEmitter.
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//
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// FIXME: This is a total hack designed to allow work on llvm-mc to proceed
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// without being blocked on various cleanups needed to support a clean interface
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// to instruction encoding.
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//
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// Look away!
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#include "llvm/DerivedTypes.h"
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namespace {
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class MCSingleInstructionCodeEmitter : public MachineCodeEmitter {
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uint8_t Data[256];
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public:
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MCSingleInstructionCodeEmitter() { reset(); }
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void reset() {
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BufferBegin = Data;
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BufferEnd = array_endof(Data);
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CurBufferPtr = Data;
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}
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StringRef str() {
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return StringRef(reinterpret_cast<char*>(BufferBegin),
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CurBufferPtr - BufferBegin);
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}
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virtual void startFunction(MachineFunction &F) {}
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virtual bool finishFunction(MachineFunction &F) { return false; }
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virtual void emitLabel(uint64_t LabelID) {}
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virtual void StartMachineBasicBlock(MachineBasicBlock *MBB) {}
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virtual bool earlyResolveAddresses() const { return false; }
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virtual void addRelocation(const MachineRelocation &MR) { }
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virtual uintptr_t getConstantPoolEntryAddress(unsigned Index) const {
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return 0;
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}
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virtual uintptr_t getJumpTableEntryAddress(unsigned Index) const {
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return 0;
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}
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virtual uintptr_t getMachineBasicBlockAddress(MachineBasicBlock *MBB) const {
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return 0;
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}
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virtual uintptr_t getLabelAddress(uint64_t LabelID) const {
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return 0;
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}
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virtual void setModuleInfo(MachineModuleInfo* Info) {}
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};
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class X86MCCodeEmitter : public MCCodeEmitter {
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X86MCCodeEmitter(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
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void operator=(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
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private:
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X86TargetMachine &TM;
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llvm::Function *DummyF;
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TargetData *DummyTD;
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mutable llvm::MachineFunction *DummyMF;
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llvm::MachineBasicBlock *DummyMBB;
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MCSingleInstructionCodeEmitter *InstrEmitter;
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Emitter<MachineCodeEmitter> *Emit;
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public:
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X86MCCodeEmitter(X86TargetMachine &_TM) : TM(_TM) {
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// Verily, thou shouldst avert thine eyes.
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const llvm::FunctionType *FTy =
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FunctionType::get(llvm::Type::getVoidTy(getGlobalContext()), false);
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DummyF = Function::Create(FTy, GlobalValue::InternalLinkage);
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DummyTD = new TargetData("");
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DummyMF = new MachineFunction(DummyF, TM);
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DummyMBB = DummyMF->CreateMachineBasicBlock();
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InstrEmitter = new MCSingleInstructionCodeEmitter();
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Emit = new Emitter<MachineCodeEmitter>(TM, *InstrEmitter,
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*TM.getInstrInfo(),
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*DummyTD, false);
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}
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~X86MCCodeEmitter() {
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delete Emit;
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delete InstrEmitter;
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delete DummyMF;
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delete DummyF;
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}
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bool AddRegToInstr(const MCInst &MI, MachineInstr *Instr,
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unsigned Start) const {
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if (Start + 1 > MI.getNumOperands())
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return false;
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const MCOperand &Op = MI.getOperand(Start);
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if (!Op.isReg()) return false;
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Instr->addOperand(MachineOperand::CreateReg(Op.getReg(), false));
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return true;
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}
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bool AddImmToInstr(const MCInst &MI, MachineInstr *Instr,
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unsigned Start) const {
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if (Start + 1 > MI.getNumOperands())
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return false;
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const MCOperand &Op = MI.getOperand(Start);
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if (Op.isImm()) {
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Instr->addOperand(MachineOperand::CreateImm(Op.getImm()));
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return true;
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}
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if (!Op.isMCValue())
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return false;
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// FIXME: Relocation / fixup.
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Instr->addOperand(MachineOperand::CreateImm(0));
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return true;
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}
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bool AddLMemToInstr(const MCInst &MI, MachineInstr *Instr,
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unsigned Start) const {
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return (AddRegToInstr(MI, Instr, Start + 0) &&
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AddImmToInstr(MI, Instr, Start + 1) &&
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AddRegToInstr(MI, Instr, Start + 2) &&
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AddImmToInstr(MI, Instr, Start + 3));
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}
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bool AddMemToInstr(const MCInst &MI, MachineInstr *Instr,
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unsigned Start) const {
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return (AddRegToInstr(MI, Instr, Start + 0) &&
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AddImmToInstr(MI, Instr, Start + 1) &&
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AddRegToInstr(MI, Instr, Start + 2) &&
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AddImmToInstr(MI, Instr, Start + 3) &&
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AddRegToInstr(MI, Instr, Start + 4));
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}
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void EncodeInstruction(const MCInst &MI, raw_ostream &OS) const {
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// Don't look yet!
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// Convert the MCInst to a MachineInstr so we can (ab)use the regular
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// emitter.
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const X86InstrInfo &II = *TM.getInstrInfo();
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const TargetInstrDesc &Desc = II.get(MI.getOpcode());
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MachineInstr *Instr = DummyMF->CreateMachineInstr(Desc, DebugLoc());
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DummyMBB->push_back(Instr);
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unsigned Opcode = MI.getOpcode();
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unsigned NumOps = MI.getNumOperands();
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unsigned CurOp = 0;
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if (NumOps > 1 && Desc.getOperandConstraint(1, TOI::TIED_TO) != -1) {
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Instr->addOperand(MachineOperand::CreateReg(0, false));
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++CurOp;
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} else if (NumOps > 2 &&
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Desc.getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
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// Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
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--NumOps;
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bool OK = true;
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switch (Desc.TSFlags & X86II::FormMask) {
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case X86II::MRMDestReg:
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case X86II::MRMSrcReg:
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// Matching doesn't fill this in completely, we have to choose operand 0
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// for a tied register.
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OK &= AddRegToInstr(MI, Instr, 0); CurOp++;
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OK &= AddRegToInstr(MI, Instr, CurOp++);
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if (CurOp < NumOps)
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OK &= AddImmToInstr(MI, Instr, CurOp);
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break;
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case X86II::RawFrm:
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if (CurOp < NumOps) {
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// Hack to make branches work.
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if (!(Desc.TSFlags & X86II::ImmMask) &&
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MI.getOperand(0).isMCValue() &&
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MI.getOperand(0).getMCValue().getSymA() &&
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!MI.getOperand(0).getMCValue().getSymB())
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Instr->addOperand(MachineOperand::CreateMBB(DummyMBB));
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else
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OK &= AddImmToInstr(MI, Instr, CurOp);
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}
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break;
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case X86II::AddRegFrm:
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OK &= AddRegToInstr(MI, Instr, CurOp++);
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if (CurOp < NumOps)
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OK &= AddImmToInstr(MI, Instr, CurOp);
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break;
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case X86II::MRM0r: case X86II::MRM1r:
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case X86II::MRM2r: case X86II::MRM3r:
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case X86II::MRM4r: case X86II::MRM5r:
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case X86II::MRM6r: case X86II::MRM7r:
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// Matching doesn't fill this in completely, we have to choose operand 0
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// for a tied register.
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OK &= AddRegToInstr(MI, Instr, 0); CurOp++;
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if (CurOp < NumOps)
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OK &= AddImmToInstr(MI, Instr, CurOp);
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break;
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case X86II::MRM0m: case X86II::MRM1m:
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case X86II::MRM2m: case X86II::MRM3m:
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case X86II::MRM4m: case X86II::MRM5m:
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case X86II::MRM6m: case X86II::MRM7m:
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OK &= AddMemToInstr(MI, Instr, CurOp); CurOp += 5;
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if (CurOp < NumOps)
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OK &= AddImmToInstr(MI, Instr, CurOp);
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break;
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case X86II::MRMSrcMem:
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OK &= AddRegToInstr(MI, Instr, CurOp++);
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if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
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Opcode == X86::LEA16r || Opcode == X86::LEA32r)
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OK &= AddLMemToInstr(MI, Instr, CurOp);
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else
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OK &= AddMemToInstr(MI, Instr, CurOp);
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break;
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case X86II::MRMDestMem:
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OK &= AddMemToInstr(MI, Instr, CurOp); CurOp += 5;
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OK &= AddRegToInstr(MI, Instr, CurOp);
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break;
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default:
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case X86II::MRMInitReg:
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case X86II::Pseudo:
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OK = false;
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break;
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}
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if (!OK) {
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errs() << "couldn't convert inst '";
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MI.print(errs());
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errs() << "' to machine instr:\n";
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Instr->dump();
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}
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InstrEmitter->reset();
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if (OK)
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Emit->emitInstruction(*Instr, &Desc);
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OS << InstrEmitter->str();
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Instr->eraseFromParent();
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}
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};
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}
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// Ok, now you can look.
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MCCodeEmitter *llvm::createX86MCCodeEmitter(const Target &,
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TargetMachine &TM) {
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return new X86MCCodeEmitter(static_cast<X86TargetMachine&>(TM));
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}
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@ -47,6 +47,10 @@ extern "C" void LLVMInitializeX86Target() {
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// Register the target asm info.
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RegisterAsmInfoFn A(TheX86_32Target, createMCAsmInfo);
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RegisterAsmInfoFn B(TheX86_64Target, createMCAsmInfo);
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// Register the code emitter.
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TargetRegistry::RegisterCodeEmitter(TheX86_32Target, createX86MCCodeEmitter);
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TargetRegistry::RegisterCodeEmitter(TheX86_64Target, createX86MCCodeEmitter);
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}
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