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[AIX] Refactor AIX Call Lowering to use CCState. NFCI.
This patch reworks the AIX call lowering to use CCState. Some defensive errors are added in this patch to protect from emitting bad code for calling convention logic that has not been implemented by design. The use of CCState follows the precedent of other targets and enables the reuse of calling convention logic in LowerFormalArguments, which will be rewritten to also use CCState in a late patch. Patch by Chris Bowler. Differential Revision: https://reviews.llvm.org/D69101
This commit is contained in:
Sean Fertile
parent
dade0c388c
commit
9aa42cfd01
@ -6695,6 +6695,79 @@ SDValue PPCTargetLowering::LowerCall_Darwin(
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NumBytes, Ins, InVals, CS);
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}
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static bool CC_AIX(unsigned ValNo, MVT ValVT, MVT LocVT,
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CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
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CCState &State) {
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if (ValVT == MVT::f128)
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report_fatal_error("f128 is unimplemented on AIX.");
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if (ArgFlags.isByVal())
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report_fatal_error("Passing structure by value is unimplemented.");
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if (ArgFlags.isSRet())
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report_fatal_error("Struct return arguments are unimplemented.");
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if (ArgFlags.isNest())
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report_fatal_error("Nest arguments are unimplemented.");
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const PPCSubtarget &Subtarget = static_cast<const PPCSubtarget &>(
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State.getMachineFunction().getSubtarget());
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const bool IsPPC64 = Subtarget.isPPC64();
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const unsigned PtrByteSize = IsPPC64 ? 8 : 4;
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static const MCPhysReg GPR_32[] = {// 32-bit registers.
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PPC::R3, PPC::R4, PPC::R5, PPC::R6,
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PPC::R7, PPC::R8, PPC::R9, PPC::R10};
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static const MCPhysReg GPR_64[] = {// 64-bit registers.
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PPC::X3, PPC::X4, PPC::X5, PPC::X6,
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PPC::X7, PPC::X8, PPC::X9, PPC::X10};
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// Arguments always reserve parameter save area.
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switch (ValVT.SimpleTy) {
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default:
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report_fatal_error("Unhandled value type for argument.");
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case MVT::i64:
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// i64 arguments should have been split to i32 for PPC32.
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assert(IsPPC64 && "PPC32 should have split i64 values.");
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LLVM_FALLTHROUGH;
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case MVT::i1:
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case MVT::i32:
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State.AllocateStack(PtrByteSize, PtrByteSize);
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if (unsigned Reg = State.AllocateReg(IsPPC64 ? GPR_64 : GPR_32)) {
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MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32;
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// Promote integers if needed.
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if (ValVT.getSizeInBits() < RegVT.getSizeInBits())
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LocInfo = ArgFlags.isSExt() ? CCValAssign::LocInfo::SExt
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: CCValAssign::LocInfo::ZExt;
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State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, RegVT, LocInfo));
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}
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else
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report_fatal_error("Handling of placing parameters on the stack is "
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"unimplemented!");
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return false;
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case MVT::f32:
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case MVT::f64: {
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// Parameter save area (PSA) is reserved even if the float passes in fpr.
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const unsigned StoreSize = LocVT.getStoreSize();
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// Floats are always 4-byte aligned in the PSA on AIX.
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// This includes f64 in 64-bit mode for ABI compatibility.
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State.AllocateStack(IsPPC64 ? 8 : StoreSize, 4);
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if (unsigned Reg = State.AllocateReg(FPR))
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State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, MVT::f64, LocInfo));
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else
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report_fatal_error("Handling of placing parameters on the stack is "
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"unimplemented!");
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// f32 reserves 1 GPR in both PPC32 and PPC64.
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// f64 reserves 2 GPRs in PPC32 and 1 GPR in PPC64.
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for (unsigned i = 0; i < StoreSize; i += PtrByteSize)
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State.AllocateReg(IsPPC64 ? GPR_64 : GPR_32);
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return false;
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}
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}
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}
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SDValue PPCTargetLowering::LowerCall_AIX(
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SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg,
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@ -6705,22 +6778,35 @@ SDValue PPCTargetLowering::LowerCall_AIX(
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SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
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ImmutableCallSite CS) const {
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assert((CallConv == CallingConv::C || CallConv == CallingConv::Fast) &&
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"Unimplemented calling convention!");
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assert((CallConv == CallingConv::C ||
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CallConv == CallingConv::Cold ||
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CallConv == CallingConv::Fast) && "Unexpected calling convention!");
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if (isVarArg || isPatchPoint)
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report_fatal_error("This call type is unimplemented on AIX.");
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EVT PtrVT = getPointerTy(DAG.getDataLayout());
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bool isPPC64 = PtrVT == MVT::i64;
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unsigned PtrByteSize = isPPC64 ? 8 : 4;
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unsigned NumOps = Outs.size();
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if (!isFunctionGlobalAddress(Callee) && !isa<ExternalSymbolSDNode>(Callee))
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report_fatal_error("Handling of indirect call is unimplemented!");
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const PPCSubtarget& Subtarget =
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static_cast<const PPCSubtarget&>(DAG.getSubtarget());
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if (Subtarget.hasQPX())
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report_fatal_error("QPX is not supported on AIX.");
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if (Subtarget.hasAltivec())
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report_fatal_error("Altivec support is unimplemented on AIX.");
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// Count how many bytes are to be pushed on the stack, including the linkage
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// area, parameter list area.
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// On XCOFF, we start with 24/48, which is reserved space for
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MachineFunction &MF = DAG.getMachineFunction();
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
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// Reserve space for the linkage save area (LSA) on the stack.
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// In both PPC32 and PPC64 there are 6 reserved slots in the LSA:
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// [SP][CR][LR][2 x reserved][TOC].
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unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
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// The LSA is 24 bytes (6x4) in PPC32 and 48 bytes (6x8) in PPC64.
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const unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
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const unsigned PtrByteSize = Subtarget.isPPC64() ? 8 : 4;
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CCInfo.AllocateStack(LinkageSize, PtrByteSize);
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CCInfo.AnalyzeCallOperands(Outs, CC_AIX);
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// The prolog code of the callee may store up to 8 GPR argument registers to
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// the stack, allowing va_start to index over them in memory if the callee
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@ -6728,98 +6814,37 @@ SDValue PPCTargetLowering::LowerCall_AIX(
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// Because we cannot tell if this is needed on the caller side, we have to
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// conservatively assume that it is needed. As such, make sure we have at
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// least enough stack space for the caller to store the 8 GPRs.
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unsigned NumBytes = LinkageSize + 8 * PtrByteSize;
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const unsigned MinParameterSaveAreaSize = 8 * PtrByteSize;
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const unsigned NumBytes = LinkageSize + MinParameterSaveAreaSize;
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// Adjust the stack pointer for the new arguments...
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// These operations are automatically eliminated by the prolog/epilog
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// inserter pass.
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// These operations are automatically eliminated by the prolog/epilog pass.
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Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
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SDValue CallSeqStart = Chain;
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static const MCPhysReg GPR_32[] = { // 32-bit registers.
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PPC::R3, PPC::R4, PPC::R5, PPC::R6,
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PPC::R7, PPC::R8, PPC::R9, PPC::R10
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};
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static const MCPhysReg GPR_64[] = { // 64-bit registers.
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PPC::X3, PPC::X4, PPC::X5, PPC::X6,
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PPC::X7, PPC::X8, PPC::X9, PPC::X10
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};
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const unsigned NumGPRs = isPPC64 ? array_lengthof(GPR_64)
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: array_lengthof(GPR_32);
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const unsigned NumFPRs = array_lengthof(FPR);
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assert(NumFPRs == 13 && "Only FPR 1-13 could be used for parameter passing "
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"on AIX");
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const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
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unsigned GPR_idx = 0, FPR_idx = 0;
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SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
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if (isTailCall)
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report_fatal_error("Handling of tail call is unimplemented!");
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int SPDiff = 0;
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for (CCValAssign &VA : ArgLocs) {
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SDValue Arg = OutVals[VA.getValNo()];
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for (unsigned i = 0; i != NumOps; ++i) {
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SDValue Arg = OutVals[i];
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ISD::ArgFlagsTy Flags = Outs[i].Flags;
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// Promote integers if needed.
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if (Arg.getValueType() == MVT::i1 ||
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(isPPC64 && Arg.getValueType() == MVT::i32)) {
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unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
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Arg = DAG.getNode(ExtOp, dl, PtrVT, Arg);
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switch (VA.getLocInfo()) {
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default: report_fatal_error("Unexpected argument extension type.");
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case CCValAssign::Full: break;
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case CCValAssign::ZExt:
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Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
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break;
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case CCValAssign::SExt:
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Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
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break;
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}
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// Note: "by value" is code for passing a structure by value, not
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// basic types.
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if (Flags.isByVal())
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report_fatal_error("Passing structure by value is unimplemented!");
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if (VA.isRegLoc())
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RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
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switch (Arg.getSimpleValueType().SimpleTy) {
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default: llvm_unreachable("Unexpected ValueType for argument!");
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case MVT::i1:
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case MVT::i32:
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case MVT::i64:
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if (GPR_idx != NumGPRs)
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RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
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else
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if (VA.isMemLoc())
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report_fatal_error("Handling of placing parameters on the stack is "
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"unimplemented!");
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break;
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case MVT::f32:
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case MVT::f64:
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if (FPR_idx != NumFPRs) {
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RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
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// If we have any FPRs remaining, we may also have GPRs remaining.
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// Args passed in FPRs consume 1 or 2 (f64 in 32 bit mode) available
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// GPRs.
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if (GPR_idx != NumGPRs)
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++GPR_idx;
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if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64)
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++GPR_idx;
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} else
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report_fatal_error("Handling of placing parameters on the stack is "
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"unimplemented!");
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break;
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case MVT::v4f32:
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case MVT::v4i32:
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case MVT::v8i16:
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case MVT::v16i8:
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case MVT::v2f64:
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case MVT::v2i64:
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case MVT::v1i128:
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case MVT::f128:
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case MVT::v4f64:
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case MVT::v4i1:
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report_fatal_error("Handling of this parameter type is unimplemented!");
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}
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}
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if (!isFunctionGlobalAddress(Callee) &&
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!isa<ExternalSymbolSDNode>(Callee))
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report_fatal_error("Handling of indirect call is unimplemented!");
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// Build a sequence of copy-to-reg nodes chained together with token chain
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// and flag operands which copy the outgoing args into the appropriate regs.
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@ -6829,10 +6854,11 @@ SDValue PPCTargetLowering::LowerCall_AIX(
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InFlag = Chain.getValue(1);
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}
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const int SPDiff = 0;
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return FinishCall(CallConv, dl, isTailCall, isVarArg, isPatchPoint,
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/* unused except on PPC64 ELFv1 */ false, DAG,
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RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
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NumBytes, Ins, InVals, CS);
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/* unused except on PPC64 ELFv1 */ false, DAG, RegsToPass,
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InFlag, Chain, CallSeqStart, Callee, SPDiff, NumBytes, Ins,
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InVals, CS);
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}
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bool
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16
test/CodeGen/PowerPC/aix-byval-param.ll
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16
test/CodeGen/PowerPC/aix-byval-param.ll
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@ -0,0 +1,16 @@
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; RUN: not llc -mtriple powerpc-ibm-aix-xcoff < %s 2>&1 | FileCheck %s
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; RUN: not llc -mtriple powerpc64-ibm-aix-xcoff < %s 2>&1 | FileCheck %s
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%struct.S = type { i32, i32 }
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define void @bar() {
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entry:
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%s1 = alloca %struct.S, align 4
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%agg.tmp = alloca %struct.S, align 4
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call void @foo(%struct.S* byval(%struct.S) align 4 %agg.tmp)
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ret void
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}
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declare void @foo(%struct.S* byval(%struct.S) align 4)
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; CHECK: LLVM ERROR: Passing structure by value is unimplemented.
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13
test/CodeGen/PowerPC/aix-nest-param.ll
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13
test/CodeGen/PowerPC/aix-nest-param.ll
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@ -0,0 +1,13 @@
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; RUN: not llc -mtriple powerpc-ibm-aix-xcoff < %s 2>&1 | FileCheck %s
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; RUN: not llc -mtriple powerpc64-ibm-aix-xcoff < %s 2>&1 | FileCheck %s
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define i8* @nest_receiver(i8* nest %arg) nounwind {
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ret i8* %arg
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}
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define i8* @nest_caller(i8* %arg) nounwind {
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%result = call i8* @nest_receiver(i8* nest %arg)
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ret i8* %result
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}
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; CHECK: LLVM ERROR: Nest arguments are unimplemented.
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15
test/CodeGen/PowerPC/aix-sret-param.ll
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15
test/CodeGen/PowerPC/aix-sret-param.ll
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@ -0,0 +1,15 @@
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; RUN: not llc -mtriple powerpc-ibm-aix-xcoff < %s 2>&1 | FileCheck %s
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; RUN: not llc -mtriple powerpc64-ibm-aix-xcoff < %s 2>&1 | FileCheck %s
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%struct.S = type { i32 }
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define void @barv() {
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entry:
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%tmp = alloca %struct.S, align 4
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call void @foo(%struct.S* sret %tmp)
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ret void
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}
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declare void @foo(%struct.S* sret)
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; CHECK: LLVM ERROR: Struct return arguments are unimplemented.
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12
test/CodeGen/PowerPC/aix-stackargs.ll
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12
test/CodeGen/PowerPC/aix-stackargs.ll
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@ -0,0 +1,12 @@
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; RUN: not llc -mtriple powerpc-ibm-aix-xcoff < %s 2>&1 | FileCheck %s
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; RUN: not llc -mtriple powerpc64-ibm-aix-xcoff < %s 2>&1 | FileCheck %s
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define void @bar() {
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entry:
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call void @foo(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9)
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ret void
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}
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declare void @foo(i32, i32, i32, i32, i32, i32, i32, i32, i32)
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; CHECK: LLVM ERROR: Handling of placing parameters on the stack is unimplemented!
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